Psuedo-microprogramming in microprocessor in single-chip micropr

Details Psuedo-microprogramming in microprocessor in single-chip micropr Psuedo-microprogramming in microprocessor in single-chip micropr

1980-11-24

1984-05-22

Thomas, James D.

Boots, shoes, and leggings

G06F 900, G06F 1300, G06F 944

Patent

active

044505191

ABSTRACT:
A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register (IR) with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM) is provided which allows execution of instruction sequences to emulate complex instructions or interpretors (macro-instructions). The macro-instructions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. This on-chip memory does not affect the off-chip main memory map. Microprocessors are thus made more versatile and can be customized with little design effort.

REFERENCES:
patent: 4004281 (1977-01-01), Bennett et al.
patent: 4153933 (1979-05-01), Blume, Jr. et al.
patent: 4181938 (1980-01-01), Suzuki et al.
patent: 4222103 (1980-09-01), Chamberlain
patent: 4368515 (1983-01-01), Nielsen
patent: 4371931 (1983-02-01), Catiller et al.

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