PSK RSFQ output interface

Details PSK RSFQ output interface PSK RSFQ output interface

2003-04-18

2004-06-29

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

With particular solid state devices

C341S155000, C375S376000, C713S400000, C331S011000, C331S012000

Reexamination Certificate

active

06756925

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to circuit devices, and more particularly to a superconducting encoder output interface device.
BACKGROUND OF THE INVENTION
There is an ever increasing demand for faster digital circuits. Traditional semiconductor electronic devices have been unable to adequately provide the desired speed for transmitting signals from high speed digital interface devices operating in frequencies above the gigahertz range (e.g., microwave frequencies). For example, conventional semiconductor technologies can handle multi-gigabit frequencies only if broad parallel circuits are utilized between interface devices. The broad parallel circuits consume unacceptable power levels in addition to increasing the complexity of the devices due to the serial-to-parallel conversions required, and the multiple line connections between units. A recent alternative to traditional semiconductor devices is superconductor electronics. Superconductor electronics provide logic devices that can achieve very high clock frequencies in the order of hundreds of gigahertz.
A library of Rapid Single-Flux-Quantum (“RSFQ”) devices have been developed over the past few years in order to provide ultrafast processing at low power consumption. RSFQ devices store and process digital bits in the form of single quanta of magnetic flux &phgr;
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transferring them in the form of short Single-Flux-Quantum (“SFQ”) pulses V(t), for example, having a quantized area ∫V(t)dt≈2 mV·pS. This data representation allows RSFQ logic to achieve extremely high clock frequencies. Due to their ability to provide ultrafast processing at low power consumption, the use of RSFQ circuits in digital systems has become increasingly desirable.
However, RSFQ circuits have a much lower signal level (e.g., about 0.5 mV to about 2.0 mV) compared to conventional semiconductor devices. For example, a simple SFQ/DC converter will convert a Return-to-Zero (“RZ”) SFQ signal into an output dc voltage. The signal will then need to be amplified by several orders of magnitude before it can be transmitted over a transmission line to non-superconducting devices. A significant problem with such signal amplification lies in the fact that the output voltage signal may become contaminated by a non-zero DC component that introduces noise into the transmitted signal that can overcome or swamp the desired signal. One approach to providing a clean output signal lies in the use of encoding the signal to mitigate the amplification of the non-zero DC component prior to amplification. Phase-Shift-Keying (“PSK”) or Manchester coding is one alternative to the encoding of a signal prior to amplification. The main attraction of PSK coding lies in the fact that while it contains a strong timing component, PSK coding contains a zero DC spectral component. In PSK coded data, data representing a digital one is transmitted at one particular phase, while data representing a digital zero is transmitted at another particular phase. Additionally, the encoded data signal then needs to be mixed with a high speed clock via a mixer, so that the data signal can be transmitted over the transmission line at very high speeds (e.g., several hundred megabits/sec).
Methods to introduce phase shifts for digital encoding prior to signal transmission are not flexible. Present methods to change data rates and phase delays are cumbersome. Encoding requires the ability to control the delay of a clock signal. For example, some of these methods require tuning the clock frequency and/or fixing the delay line length. Fixed-length delay lines on the other hand, have a restricted range of data rate. One mechanism to employ phase shifting for digital decoding is to run a clock through a phase shifter. The phase shifter generates the I component (in-phase) and Q component (quadrature phase) of the signal and employs a multiplexer to toggle between the phases. The phase shifter is limited in both the frequency bandwidth and the phase shift since the device is designed to provide a fixed frequency band and a fixed phase shift. Additionally, the phase shifter can be quite large, in the order of centimeters in size, and the size of the phase shifter increases with the lowering of the frequency. Furthermore, some phase shifters employ magnetic materials, which affect the performance of superconducting circuits, and therefore, phase shifters are not readily integrated with superconductor devices, thus limiting the speed of the transmission. Another conventional method can include employing a counter or clock through a coaxial cable or transmission line at different lengths to introduce a phase shift prior to transmission. Additionally, this method has limitations since the fixed coaxial cable or transmission line lengths are designed to provide a fixed frequency bandwidth and fixed phase shift.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
A Rapid Single-Flux-Quantum (RSFQ) encoder output interface device is provided. The RSFQ output interface device includes a RSFQ variable phase multi-junction voltage controlled oscillator (VCO) that provides multiple clock signals having substantially equal frequencies and variable phase delays, such that the clock function and the phase delay are integrated into a single device. The clock output signals generate Single-Flux-Quantum (SFQ) voltage pulses. The frequency of the multiple clock signals are based on a DC bias current setting. The multiple clock signals are phase shifted from one another based on a flux bias current setting. A fixed DC bias current source can be employed to provide a fixed clock signal frequency. Alternatively, a variable DC bias current source can be employed to provide a variable clock signal frequency. A fixed flux bias current source can be employed to provide a fixed phase delay between clock signals, and a variable flux bias current source can be employed to provide a variable phase delay between clock signals. The fixed current sources can be set to provide data encoded output in Phase-Shift-Keying (PSK) coding format, such as binary PSK (BPSK) or quadrature PSK (QPSK). The variable current source can be employed to provide a variable encoded format based on an encoded scheme profile.
The clock signals are then mixed together according to logic states of a data stream to provide an encoded output data stream. The clock signal can be mixed together employing a multiplexer with opposing phases being provided as input to the multiplexer and the data stream being coupled to the select line of the multiplexer. The multiplexer can also be a RSFQ device that is readily compatible with the RSFQ variable phase multi-junction VCO. The SFQ voltage pulses of the encoded output data stream are converted to a voltage level appropriate for transmitting over a wire. The RSFQ encoder output interface device is well suited for integrating into a high speed network routing system, such that a RSFQ encoder output interface can be provided at each respective output of a RSFQ router device.
In one aspect of the present invention, the RSFQ variable phase multi-junction VCO is comprised of M-1 adjacent Super Conducting Quantum Interface Device (SQUID) quantizers where M is the number of output terminals or stages of the RSFQ variable phase multi-junction VCO. The SQUID quantizers each have at least one inductor disposed between a pair of Josephson junctions with adjacent SQUID quantizers sharing adjacent Josephson junctions. A DC bias current source is coupled between each of the at least one inductors associated with a respective SQUID quantizer. The DC bias current sources provi

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