Multiplex communications – Communication over free space – Having a plurality of contiguous regions served by...
Reexamination Certificate
1998-04-24
2001-08-28
Kizou, Hassan (Department: 2662)
Multiplex communications
Communication over free space
Having a plurality of contiguous regions served by...
C370S310000, C370S342000
Reexamination Certificate
active
06282181
ABSTRACT:
BACKGROUND
The present invention relates generally to radiocommunication systems and, more particularly to techniques for generating and advancing pseudorandom number sequences used in such systems.
Direct-sequence code division multiple access (DS-CDMA) is a method of communication whereby each user transmits information in a given frequency band simultaneously. Different users modulate each data bit using a unique pseudo-random spreading code. At the receiver different users' signals are separated by correlating the received signal with the spreading code of the desired user. These spreading codes are typically generated as pseudorandom sequences using shift registers and are called shift register sequences.
A maximal length shift register sequence is a sequence obtained from a shift register with a certain feedback property. These types of sequences can be described by linear recursion. For example, if S
t
is the sequence value (S
t
&egr;{0, 1}) then:
S
t
=
∑
i
=
1
m
S
t
-
i
a
i
(
1
)
where the sum is performed using modulo-2 addition and the coefficients a
i
&egr;{0, 1}. The sequences generated by this technique will vary in length. For certain sequences, the length will be 2
m
−1. If this is the case, s
t
is said to be a maximal length shift register sequence, which sequences are used as spreading codes. There are two general techniques for conventionally generating such sequences. The first way, referred to as a simple shift register generator (SSRG), is shown in FIG.
1
.
In the example of
FIG. 1
, the sequence is shifted through a plurality of delay stages
10
-
18
. The s
t
and s
t+2
terms are modulo-2 added together at block
20
, such that s
t+5
=s
t
+s
t+2
, which implies s
t
=s
t−3
+s
t−5
. If the sequence is started with the shift stages in the all zero state, then the resulting sequence is identically zero. If, on the other hand, the sequence is started in state 00001, the sequence of states is:
00001
01101
00111
01110
10000
00110
00011
10111
01000
10011
10001
01011
00100
11001
11000
10101
10010
11100
01100
01010
01001
11110
10110
00101
10100
11111
11011
00010
11010
01111
11101
00001
The resulting maximal length sequence is 1000010010110011111000110111010 and has length 31.
Another conventional method used to generate the same sequence is shown in FIG.
2
. This technique is sometimes referred to as a modular shift register generator (MSRG). Like the simple shift register generator, the modular shift register generator also has a plurality of shift or delay stages
24
-
32
. However, it can be seen in
FIG. 2
that the modulo-2 adder
22
is now inserted between the second
26
and third
28
shift stages. The contents of the shift register of
FIG. 2
, using the same initial inputs as those given above for the shift register of
FIG. 1
, are:
00001
01110
00110
01101
10100
00111
00011
10010
01010
10111
10101
01001
00101
11111
11110
10000
10110
11011
01111
01000
01011
11001
10011
00100
10001
11000
11101
00010
11100
01100
11010
00001
The resulting 31 bit sequence generated is 1001011001111100011011101010000. This sequence is a cyclically shifted version of the sequence generated by the shift register generator of
FIG. 1
, i.e., an equivalent sequence.
Sometimes it is advantageous to use extended or augmented shift register sequences. For example, in the IS-95 CDMA standard, length 2
15
−1 sequences are extended by one zero chip value to obtain sequences of length 2
15
. An example of extended sequence generation in conjunction with a modular shift register generator is discussed in U.S. Pat. No. 5,228,054. Also, combinations of PN sequences can be used to form Gold sequences. Extended Gold sequences are also possible.
In portable radiocommunication devices, it is generally desirable to conserve battery power. Accordingly, such devices, e.g., mobile phones, may periodically be put into a sleep mode, for example when turned on but not in use (“idle”), wherein most of the electronics are powered shut down. The phone may be asleep for time intervals on the order of a second, so that sleep intervals correspond to many chip periods. For example, sleep mode can be used to reduce the power consumption of an idle phone, which phone “awakens” only during periods when it can receive a page, e.g. during an assigned paging frame. If a page is not received, the phone can return to the sleep mode, thereby conserving battery power.
When the phone wakes up to, e.g., listen for pages, it is desirable to properly reset the circuitry used for receiving messages. This resetting process includes producing shift register sequences having the correct state. For example, the IS-95 system state is partially determined by two shift register sequences, sometimes referred to as the short and long code sequences. For such systems, in order to properly decode messages transmitted over the paging channel, the phone needs to have the proper short and long code sequences for despreading and descrambling.
Accordingly, there is a need to efficiently advance shift register sequences by a certain number of clock cycles to accommodate, for example, deactivated circuitry during sleep modes. If the sequence is not advanced properly, received signals may not be properly despread resulting in lost pages and power consuming re-synchronization. If the sequence is advanced properly, but at a huge cost in battery power, then the standby time of the phone is greatly reduced. For example, the simplest solution for advancing a sequence generator to a future state is to clock the sequence generator until the desired state new state is reached. The clock to the sequence generator can be left on during sleep mode, so that the generator advances to the desired state when the rest of the phone wakes up. However, such an approach can be costly in battery consumption, as the sequence clock typically operates at a high clock rate and power consumption increases as the clock rate increases. Thus, a power efficient, yet accurate, technique for handling the advancement of shift register sequences after sleep mode is needed.
SUMMARY
According to the present invention, these and other drawbacks, limitations and objects of conventional pseudorandom number sequence generation techniques are overcome by efficiently advancing the shift register from one state to another state, e.g., so that the shift register is in a desired state upon exiting sleep mode. Exemplary embodiments of the present invention provide for selectable linear combinations of elements of the shift register to use the current state to compute the new state based on an arbitrary shift.
A receiver according to an exemplary embodiment of the present invention can include a processor which determines the desired, arbitrary shift and provides this information to a sequence advancing unit. The sequence advancing unit extracts the current state of the sequence generator and selectively combines matrices associated with the current state values using the arbitrary shift information to arrive at the new state. This new state can then be used to overwrite the contents of the shift register so that, for example, when the receiver awakens to investigate messages transmitted on a paging channel, the proper pseudorandom number sequences are available for despreading and descrambling.
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paten
Bottomley Gregory E.
Dent Paul W.
Stark Wayne
Coats & Bennett
Ericsson Inc
Kizou Hassan
Tsegaye Saba
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