Pseudo set-associative memory caching arrangement

Details Pseudo set-associative memory caching arrangement Pseudo set-associative memory caching arrangement

1992-06-24

1993-05-11

Fleming, Michael R.

Boots, shoes, and leggings

364DIG1, 3642434, 36424341, 364253, 3642543, G06F 1208

Patent

active

052108430

ABSTRACT:
The invention provides a pseudo set-associative memory cacheing arrangement for use in a data processing system comprising a processor interfacing to a main memory and adapted to support a cache memory. The arrangement comprises a plurality of cache memory banks each comprising a respective number of addressable locations individually defined by a cache address. A plurality of cache select circuits are each associated with a respective one of the cache memory banks and each one is responsive to m most significant bits of a main memory address and control signals for mapping its associated cache memory bank to a predetermined range of addresses in main memory.

REFERENCES:
patent: 4424561 (1984-01-01), Stanley et al.
patent: 4437149 (1984-03-01), Pomerene et al.
patent: 4441155 (1984-04-01), Fletcher et al.
patent: 4453230 (1984-06-01), Mizoguchi et al.
patent: 4467414 (1984-08-01), Akigi et al.
patent: 4493026 (1985-01-01), Olnowich
patent: 4631660 (1986-12-01), Woffiinden et al.
patent: 4667288 (1987-05-01), Keeley et al.
patent: 4736293 (1988-04-01), Patrick
patent: 4807110 (1989-02-01), Pomerene et al.

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