Pseudo-random vector generated testable counter

Details Pseudo-random vector generated testable counter Pseudo-random vector generated testable counter

1991-07-03

1995-05-02

Trans, Vincent N.

Boots, shoes, and leggings

371 27, 371 225, G01R 3128

Patent

active

054125804

ABSTRACT:
A digital counter which can be easily and thoroughly tested with a short sequence of random or pseudo-random input vectors. The counter includes a pair of pseudo-random input generators, probability regeneration logic and full scale observability logic. The counter has improved capability to detect stuck at faults in the counter full scale output gates. The counter is particularly advantageous in a VLSI circuit design.

REFERENCES:
patent: 4667301 (1987-05-01), Chiu et al.
patent: 4730319 (1988-03-01), David et al.
patent: 4789821 (1988-12-01), Baschiera et al.
patent: 4982403 (1991-01-01), Du Chene et al.
patent: 5006787 (1991-04-01), Katiricioglu et al.
patent: 5138619 (1992-08-01), Fasang et al.

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