Pseudo-random phase shifted arithmetic bit clock generators for

Details Pseudo-random phase shifted arithmetic bit clock generators for Pseudo-random phase shifted arithmetic bit clock generators for

1988-12-22

1990-06-19

Harkcom, Gary V.

Boots, shoes, and leggings

364718, G06F 102

Patent

active

049358910

ABSTRACT:
An arithmetic frequency synthesizer for generating a bit clock for the flying spot scanner of a digital printer includes means for loading a pseudo-random offset value, accm.sub.i ; into its accumulator at the start of each scan. The offset values for successive scans pseudo-randomly vary within a range 0.ltoreq.accm.sub.i <N for all bit clock frequencies required for normal operation of the printer. Thus, the offsets pseudo-randomly phase shift the phase transitions of the bit clock sufficiently to prevent periodic variations in the bit clock duty cycle from spatially aligning with each other in the process direction during the printing of adjacent scan lines.

REFERENCES:
patent: 3772681 (1973-11-01), Skingle
patent: 3973209 (1976-08-01), Nossen et al.
patent: 4134072 (1979-01-01), Bolger
patent: 4328554 (1982-05-01), Mantione
patent: 4559613 (1985-12-01), Murphy et al.
patent: 4766560 (1988-08-01), Curry et al.

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