Pseudo random pattern generation circuit

Details Pseudo random pattern generation circuit Pseudo random pattern generation circuit

1992-12-01

1994-06-14

Malzahn, David H.

Boots, shoes, and leggings

G06F 102

Patent

active

053216415

ABSTRACT:
In a pseudo random pattern generation circuit having a normal input operation mode, a boundary scanning operation mode and an inherent pseudo random pattern generation mode, output stage selectors are provided to supply input data as output data without modification in the normal input operation mode. In addition, flipflops are provided to hold the data in the boundary scanning operation mode, so that the data held in the flipflops are not supplied as output signals. Thus, in the normal input operation mode, the data processing speed is increased, and in the boundary scanning operation mode, the data just before the boundary scanning operation mode is maintained without being outputted to an internal circuit of the LSI chip.

REFERENCES:
patent: 5031130 (1991-07-01), Harada
patent: 5105376 (1992-04-01), Pedron
patent: 5187676 (1993-02-01), DeVane
patent: 5257282 (1993-10-01), Adkisson et al.

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