Pseudo-random pattern generating circuit

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G06F 102

Patent

active

056383096

ABSTRACT:
The present invention relates to pseudo-random pattern generating circuit for outputting pseudo-random patterns of a plurality of pseudo-random stages, characterized in comprising: a plurality of latch circuits for conducting delayed output of data input in synchrony with a clock input; a multiple input exclusive OR arithmetic circuit, an output of which is inputted into the aforementioned latch circuits; and a select circuit for selecting an output of the latch circuit and inputting this output as input data to the exclusive OR arithmetic circuit; wherein the select circuit switches an output to the exclusive OR arithmetic circuit according to an inputted select signal. In addition, it is also possible for the pseudo-random pattern generating circuit to further comprise a decoding circuit for converting an inputted pseudo-random selection signal to a select signal, and outputting this select signal.

REFERENCES:
patent: 5434807 (1995-07-01), Yoshida
patent: 5444645 (1995-08-01), Yoshida et al.
ICC '79 Conference Record, International Conference on Communications, Boston, MA, vol. 1/4, Jun. 10-14, 1979, IEEE New York, NY, pp. 7.5.1-7.5.4, Krystyn Plewko, et al., "Generation and Properties of Pseudorandom Binary Sequences", Institute of Telecommunications, Warsaw, Poland.

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