Boots – shoes – and leggings
Patent
1985-10-01
1988-05-31
Harkcom, Gary V.
Boots, shoes, and leggings
G06F 102
Patent
active
047485760
DESCRIPTION:
BRIEF SUMMARY
This invention relates to pseudo-random binary sequence generators.
BACKGROUND OF THE INVENTION
Pseudo-random binary sequence generators (p.r.b.s. generators) are well known and reference should be made to the book "Cypher Systems" by Beker and Piper, 1982, published by Northwood Books, London for a description of the construction and operation of such generators. In particular, such generators can take the form of linear-feedback shift registers (LFSRs) and particular reference should be made to LFSRs of the "Galois" or "dual" kind.
P.r.b.s. generators comprise essentially an n stage recirculatory shift register and one or more associated logic gates in the loop for combining the output of at least two register stages. By appropriate choice of the logic gates a repeating sequence can be obtained of length 2.sup.n -1 bits. If n is a suitably large number this sequence is very long indeed, and the bits can be regarded as random; hence the term "pseudo random".
There may be applications where it is desired to reduce the possibilities of mimicking the generator output, and thus to increase the unpredictability of both the output signal and also the contents of the shift register stages, even when the contents of some of the shift register stages may be known.
SUMMARY OF THE INVENTION
A pseudo-random binary sequence generator using a selector having data inputs and address inputs for selecting at any instant one of the data input bits in accordance with the address input word to provide the generator output. The generator includes a recirculatory shift register with at least one recirculatory loop having a plurality of logic gates for logically combining the outputs of selected stages of the loop to provide a pseudo-random sequence. Data inputs of the selector are connected to the outputs of some of the shift register stages of the loop and address inputs of the selector are connected to the outputs of others of the shift register stages of the same loop.
The invention in its various aspects is defined in the appended claims to which reference should now be made.
DESCRIPTION OF THE DRAWING
The invention will be described by way of example with reference to the drawings, in which
FIGS. 1, 2 and 3 each show a block circuit diagram of a respective p.r.b.s. generator embodying the invention, and
FIG. 4 is a block diagram of a circuit for modifying the input to the p.r.b.s. generator shown in FIGS. 1, 2 or 3.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 shows a p.r.b.s. generator which comprises two LFSRs, S and T. The register S has 29 stages S.sub.0 . . . S.sub.28 and the register T has 31 stages T.sub.0 . . . T.sub.30. In each case the output of the final stage is during normal running applied as the input to the first stage in a recirculating loop. The loop also includes a plurality of logic gates G, in the form of exclusive-OR circuits, which combine the output of the final stage with the output of one shift register stage for application to the next shift register stage.
The positions of the gates G are chosen so that the sequence generated by the register is of maximum possible length. Conventionally, the positions of the gates are described in the form of a polynomial, of the form: X.sup.n-1 +X.sup.n
Using this notation, it is seen that p.r.b.s. generator S is of the form +X.sup.20 +X.sup.29 S.sub.3, S.sub.4, S.sub.5, S.sub.7, S.sub.11, S.sub.13, S.sub.14 and S.sub.20. Thus, there are nine such gates, and each gate introduces an additional term into the polynomial.
Similarly, p.r.b.s. generator T has gates G at the inputs to stages T.sub.1, T.sub.2, T.sub.3, T.sub.5, T.sub.6, T.sub.7, T.sub.9, T.sub.10, T.sub.11, T.sub.15, T.sub.19, T.sub.23 and T.sub.27. In this case there are 13 gates.
The circuit of FIG. 1 also includes a multiplexer M, or selector circuit. This has 5 address inputs A.sub.i and 32 data inputs B.sub.i and operates to select one of the data inputs for application to the output in dependence upon the address word applied to the address inputs. More generally, where there are
REFERENCES:
patent: 3881099 (1975-04-01), Ailett et al.
patent: 4047008 (1977-09-01), Perkins
H. Beker et al, "Cipher Systems-The Protection of Communications", Northwood Publications, 1982, pp. 212, 240-246.
S. Jennings, "Multiplexed Sequences: Some Properties of the Minimum Polynomial", in Cryptography Lecture Notes in Computer Science, vol. 149, pp. 189-206, Published in Proceeding Burg Feuerstein 1982 by Springer Verlag 1983.
S. Jennings, "A Special Class of Binary Sequences", Ph. O. Thesis, Univ. of London, 1980, chapter 2, pp. 57-61 & chapter 4, pp. 156-161.
Beker Henry J.
Boes Luc Emiel L.
Brennand Peter R.
Brown Edmund R.
Crowther Gerald O.
Harkcom Gary V.
Mai Tan V.
O'Connell Robert F.
U.S. Philips Corporation
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