Pseudo push-pull DC:DC power converter topology

Details Pseudo push-pull DC:DC power converter topology Pseudo push-pull DC:DC power converter topology

2000-09-26

2001-08-07

Berhane, Adolf Deneke (Department: 2838)

Electric power conversion systems

Current conversion

Including d.c.-a.c.-d.c. converter

C363S133000

Reexamination Certificate

active

06272026

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to DC:DC power converters, and more specifically to providing a topology having the advantage of push-pull without requiring a push-pull drive that must output precise 50%:50% duty cycle drive signals.
BACKGROUND OF THE INVENTION
Circuitry to implement DC:DC converters is known in the art. Such circuits receive an input-side DC voltage that is sampled or chopped and transformer-coupled to an output side. On the output side, the waveform is rectified and filtered to provide a regulated output voltage that may be greater than or less than the input voltage. Feedback from output to input can be used to regulate the sampling duty cycle or frequency to provide an acceptably efficient DC:DC converter in a small form factor.
FIG. 1A
depicts a so-called voltage-fed push-pull DC:DC converter
10
, according to the prior art, having an input side
20
and an output side
30
, generally separated by a transformer T
1
. The input side
20
of the converter is coupled to a source of DC potential Vin. Potential Vin is shown coupled to a pre-regulator
40
whose output potential is controlled within a known tolerance. Although pre-regulator regulator
40
is depicted in the figures, in general it is optional and may be dispensed with if Vin is sufficiently controlled. The output potential from preregulator regulator
40
is sampled or chopped using push-pull switching transistors Q
1
, Q
2
and respective transformer T
1
primary windings W
1
, W
2
. As best seen in
FIG. 1B
, a control circuit
50
provides complementary drive signals to the input leads of Q
1
, Q
2
such that when Q
1
is on, Q
2
is off, and vice versa. Although Q
1
and Q
2
are shown as switching an end of primary windings W
1
, W
2
to ground potential, it is understood that ground potential implies a stable potential. Stated differently, if desired a potential other than 0 V DC might instead be switchably coupled to an end of primary windings W
1
and W
2
. This understanding that ground is simply a convenient reference potential shall apply throughout this disclosure.
Dual center-tapped secondary transformer windings are shown on output side
30
of DC:DC converter
10
, although other winding configurations could instead be used, e.g., a single center-tapped secondary winding could instead be used. Transformer T
1
's center-tapped secondaries W
3
-
1
, W
3
-
2
, and W
4
-
1
, W
4
-
2
step-up or step-down the chopped waveforms, which are rectified by diodes D
1
, D
2
and capacitor C
1
, and by diodes D
3
, D
4
and capacitor C
2
. Other rectification configurations may of course be used, e.g., full-bridge rectification using four diodes. The secondary windings may output different magnitudes Vo
1
, Vo
2
and the number of windings may be greater or less than two. In some configurations, a feedback loop (not shown) may be coupled between the secondary output voltages and control circuit
50
.
As shown in
FIG. 1B
, in an ideal case in which circuit
50
generates drive signals &thgr;
1
and &thgr;
2
that are precisely 180° out of phase, switch Q
1
will be on when Q
2
is off, and vice-versa. As a result, operating efficiency is high, and the filtering requirements on the output side are minimized in that reduction of switching transients will be the primary task of the rectification and filter circuitry. In the configuration shown, output filtering is provided by output capacitors C
1
and C
2
. If desired, inductors could also be used to provide L-C low-pass output filtering. The balanced nature of the output voltage signals and the relative minimal requirements on the output filter are beneficial features of push-pull topography.
But in practice, it is very difficult to provide an inexpensive control circuit
50
that can reliably output two perfectly complementary drive signals &thgr;
1
, &thgr;
2
. If, for example, circuit
50
outputs complementary signals that are slightly out of phase, e.g., where phase shift &Dgr; is non-zero, then there will be times of durations &Dgr; when both Q
1
and Q
2
are simultaneously on. As a result, operating efficiency will suffer, and more severe switching transients must be filtered from the Vo
1
, Vo
2
signal(s). Thus, much consideration must be given to the design and implementation of a push-pull control circuit
50
to minimize the undesired effects of overlapping drive signals. The result can be a relatively complete control circuit
50
whose component cost can be relatively large when compared to the cost of all components in the overall DC:DC converter. Further, even with an ideal control circuit, body effect diodes are inherently present in Q
1
and Q
2
, and tend to conduct unwanted current, thus decreasing circuit efficiency.
Thus, there is a need for a DC:DC converter topology that provides the efficiency and output filtering advantages associated with a true push-pull configuration, but without requiring a control circuit that can output perfectly complementary drive signals.
The present invention provides such a topology, referred to herein as a pseudo push-pull topography.
SUMMARY OF THE PRESENT INVENTION
The present invention provides a DC:DC converter topology that offers the switching efficiency and output filtering advantages of a push-pull converter, but without requiring a control circuit that can deliver perfect complementary drive signals. The invention uses a converter transformer T
1
′ with a gapped transformer core, and replaces one of the two primary switches with a passive switch such as a diode. The first and second converter transformer primary windings (W
1
, W
2
) are each coupled at one end to Vin. The second end of the first primary winding is coupled to ground (or other reference potential) via a switch Q
1
under command of a control circuit that outputs a single pulse train control signal &thgr;
1
of slightly less than 50% duty cycle. The second end of the second winding is connected to a diode DX
1
whose anode end is connected to ground (or other reference potential).
When &thgr;
1
goes high, Q
1
turns on and Vin will be coupled across primary winding W
1
. Electromagnetic energy is instantly transferred from the primary side to the secondary side of transformer T
1
′, and some electromagnetic energy will be stored within the gapped transformer core. Circuit design is such that sufficient joules of electromagnetic energy are stored in the gapped transformer core to meet the energy requirements for a predicted maximum secondary (output) load, to be delivered when Q
1
is turned off. When &thgr;
1
turns Q
1
off, a fraction of the electromagnetic energy stored in the gapped transformer core turns-on diode DX
1
, which causes Vin to be coupled across primary winding W
2
. Any excess stored electromagnetic energy not required by the secondary load will be transferred elsewhere automatically, e.g., to the primary side. Duty cycle is preferably slightly less than 50%, and DXl biases itself off before &thgr;
1
subsequently again turns-on Q
1
.
The present invention produces what is essentially a push-pull output, with the output rectification filter advantages that accompany a typical push-pull circuit. However the control circuit is simplified in that a single control signal &thgr;
1
is generated, as contrasted with the need to generate complementary non-overlapping control signals in the prior art. Further, a single switch Q
1
is required, the second switching action being performed by the diode DX
1
. The resultant topology thus offers filtering and EMI advantages of a true push-pull configuration, but without the expense and difficulty associated with generating true push-pull drive signals.
Other features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail, in conjunction with the accompanying drawings.


REFERENCES:
patent: 4408267 (1983-10-01), Pruitt
patent: 5903448 (1999-05-01), Davila, Jr.

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