Pseudo-nonvolatile memory incorporating data refresh operation

Details Pseudo-nonvolatile memory incorporating data refresh operation Pseudo-nonvolatile memory incorporating data refresh operation

1993-11-23

1996-04-23

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

36518517, 365222, 36518525, G11C 1300

Patent

active

055110207

ABSTRACT:
A pseudo nonvolatile memory cell which may be operated in a pseudo-nonvolatile mode is achieved by utilizing a thin direct tunneling dielectric adjacent to the charge retaining region in a traditional nonvolatile memory cell such as an EPROM, EEPROM, flash EPROM, or flash EEPROM cell. The use of the direct tunneling dielectric allows for greatly enhanced write/erase cycles (exceeding 100 gigacycles) and reduced data write/erase time (under 1 microsecond). The direct tunneling dielectric also results in a reduced data retention period. Consequently, refresh circuitry is provided to maintain the non-volatility of the memory cell. A back-up battery is used to power the refresh circuitry when the system power is removed. This mode of operation provides an effectively nonvolatile memory system that is suitable for replacing traditional nonvolatile memory devices.

REFERENCES:
patent: 5040036 (1991-08-01), Hazani
patent: 5140552 (1992-08-01), Yamauchi et al.
patent: 5146431 (1992-09-01), Eby et al.
patent: 5198380 (1993-03-01), Harari
patent: 5278428 (1994-01-01), Yamada
Aritome et al., "Reliability Issues of Flash Memory Cells," Proceedings of the IEEE, vol. 81, No. 5, May, 1993, pp. 776-787.
Kynett et al., "A 90ns 100K Erase/Program Cycle Megabit Flash Memory," IEEE Int'l Solid-State Circuits Conferences, Feb., 1989, pp. 140-141.
Lancaster, et al., "A 5V-Only EEPROM with Internal Program/Erase Control," Nonvolatile Semiconductor Memories, Technologies, Design, and Applications, IEEE Press Selected Reprint Series, Paper 4.7, pp. 149-151 (reprinted from IEE ISSCC Dig. Techn, Pap., 1983, pp. 164-165).
Samachisa, et al., "A 128K Flash EEPROM Using Double-Polysilicon Technology," Nonvolatile Semiconductor Memories, Technologies, Design, and Applications, IEEE Press Selected Reprint Series, Paper 5.3, pp. 176-182 (reprinted from IEEE J. Solid-State Circuits, vol. SC-22, No. 5, Oct., 1987, pp. 676-683).
Yatsuda et al., "Hi-MNOS II Technology for a 64-kbit Byte-Erasable 5-V-Only EEPROM," Nonvolatile Semiconductor Memories, Technologies, Design, and Applications, IEEE Press Selected Reprint Series, Paper 4.8, pp. 152-159 (reprinted from IEEE Journal of Solid-State Circuits, vol. SC-20, No. 1, Feb., 1985, pp. 144-151).

Affiliated with

Also associated with

Rating

Pseudo-nonvolatile memory incorporating data refresh operation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pseudo-nonvolatile memory incorporating data refresh operation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pseudo-nonvolatile memory incorporating data refresh operation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2314572