Pseudo-memory circuit for testing for stuck open faults

Details Pseudo-memory circuit for testing for stuck open faults Pseudo-memory circuit for testing for stuck open faults

1987-04-06

1988-05-03

Eisenzopf, Reinhard J.

Electricity: measuring and testing

Plural, automatically sequential tests

371 25, G01R 3128

Patent

active

047422939

ABSTRACT:
A method and apparatus are disclosed for testing for stuck- open faults in integrated circuits (10) having a plurality of combinational logic devices (18, 20). The apparatus includes a chain of shift register stages (22), with each stage including at least two latches (L1 and L3). The bits of an initialization test are shifted down the shift register and loaded into one of the latches (L3), while the bits of a detection test pattern are subsequently shifted down the chain and stored in the other latch (L1). A multiplexer (50) is provided for selecting one of the outputs from the two latches (L1, L3) so that the initialization test pattern and then the detection test pattern can be quickly applied to the combinational logic so as to minimize hazards which could invalidate the test results.

REFERENCES:
patent: 4697279 (1987-09-01), Baratti et al.
patent: 4703257 (1987-10-01), Nishida et al.
Intl. Test Conference, Nov. 1985, Craig et al., "Pseudo-Exhaustive Adjacency Testing . . . ", pp. 126-137.

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