Pseudo line locked write clock for picture-in-picture video appl

Details Pseudo line locked write clock for picture-in-picture video appl Pseudo line locked write clock for picture-in-picture video appl

1988-09-07

1990-11-13

Chin, Tommy P.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358 22, 358149, H04N 5275

Patent

active

049705962

ABSTRACT:
The write clock controlling operation of the PIP circuitry (e.g. the analog digital converter in the PIP channel) utilizes a clock signal source having a substantially higher frequency (preferably six times) the desired write clock frequency. This clock signal is applied to a divide by six circuit which has a cycle reset controlled by the horizontal synchronization signal of the incoming PIP signal. The write clock signal furnished by this arrangement has the correct rate for sampling the incoming PIP video information and is pseudo line locked to the PIP horizontal synchronization signal.

REFERENCES:
patent: 3984633 (1976-10-01), Rutt
patent: 4199788 (1980-04-01), Tsujimura
patent: 4228433 (1980-10-01), Matsumoto
patent: 4238773 (1980-12-01), Tsuboka et al.
patent: 4617594 (1986-10-01), Katagiri
patent: 4665438 (1987-05-01), Miron
patent: 4736162 (1988-04-01), Ishihara

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