Pseudo-exhaustive self-test technique

Details Pseudo-exhaustive self-test technique Pseudo-exhaustive self-test technique

1992-08-26

1995-10-10

Baker, Stephen M.

Excavating

371224, 371 27, G01R 313183, G01R 313185

Patent

active

054576970

ABSTRACT:
Pseudo-exhaustive self-testing of an electronic circuit (10), containing groups of combinational elements (14.sub.1,14.sub.2, 14.sub.3 . . . 14.sub.n), is accomplished by first partitioning the groups of combinational elements into sub-cones having no more than w inputs each by designating appropriate nodes ("test points") in each cone as the output of a sub-cone. A set of test vectors {a.sub.1, a.sub.2 . . . a.sub.w, b.sub.1, b.sub.2 . . . b.sub.w } is then generated (via an internal generator 74) such that when the vectors are applied to the sub-cones (14.sub.1.sbsb.a, 14.sub.1.sbsb.b . . . . 14.sub.i.sbsb.j), each sub-cone will be exhaustively tested. Each of the inputs of the sub-cones is assigned to receive a vector such that the vectors received at the inputs are linearly independent. The subset of vectors is applied through each of a plurality of pseudo-exhaustive self-test (PEST) flip-flop circuits (88) and through the test points to test the circuit. The PEST flip-flop circuits 88 also serve to advantageously compact and observe the response data produced by each sub-cone (14.sub.i.sbsb.j) with that of an upstream sub-cone.

REFERENCES:
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