Excavating
Patent
1990-02-26
1993-02-16
Baker, Stephen M.
Excavating
371 225, 371 27, G01R 3128
Patent
active
051877120
ABSTRACT:
Psuedo-exhaustive self-testing of an electronic circuit (10), containing groups of combinational elements (14.sub.1, 14.sub.2, 14.sub.3 . . . 14.sub.n), is accomplished by first partitioning the groups of combinational elements into sub-cones having no more than w imputs each by designating appropriate nodes ("test points") in each cone as the output of a sub-cone. A set of test vectors {a.sub.1, a.sub.2 . . . a.sub.w, b.sub.1, b.sub.2 . . . b.sub.w } is then generated (via an internal generator 74) such that when the vectors are applied to the sub-cones (14.sub.1.sbsb.a, 14.sub.1.sbsb.b . . . . 14.sub.i.sbsb.j), each sub-cone will be exhaustively tested. Each of the inputs of the sub-cones is assigned to receive a vector such that the vectors received at the inputs are linearly independent. The subset of vectors is applied through each of a plurality of pseudo-exhaustive self-test (PEST) flip-flop circuits (88) and through the test points to test the circuit. The PEST flip-flop circuits 88 also serve to advantageously compact and observe the response data produced by each sub-cone (14.sub.i.sbsb.j) with that of an upstream sub-cone.
REFERENCES:
Roberts, M. et al., "An Algorithm for the Partitioning of Logic Circuits", IEE Proc., vol. 131, Pt.E, No. 4, Jul. 1984, pp. 113-118.
E. J. McCluskey and S. Bozorgui-Nesbat, "Design for Autonomous Test", IEEE Transactions on Computers, vol. C-30, No. 11, Nov. 1981, pp. 866-875.
S. B. Akers, "On the Use of Linear Sums in Exhaustive Testing", Proceedings, Fault Tolerant Computing Conference, pp. 148-163 (IEEE), 1985.
E. Wu, "Towards an Optimal Pseudo-Exhaustive Test Generation Algorithm", Conference Proceedings, Built-In Self-Test Workshop. IEEE Test Technology Committee, Mar. 23-25, 1988.
IEE Publication, "Review of Built-In Test Methodologies and Gate Arrays", by K. A. E. Totton, IEE Proceedings I. Solid-State and Electron Devices, vol. 132, Parts E and I, No. 2, Mar./Apr. 1985, pp. 121-129, Stevenage, Great Britain.
IEEE Publication "PEST, a Tool for Implementing Pseudo-Exhaustive Self-Test", by E. Wu, Proceedings of the IEEE 1990 Custom Integrated Circuits Conference, Boston, Mass., May 13-16, 1990, pp. 28.4.1-28.4.3.
IEEE Publication "Automated BIST for Sequential Logic Synthesis", by C. E. Stroud IEEE Design & Test of Computers, vol. 5, No. 6+index, Dec. 1988, pp. 22-23 New York, N.Y.
EPO Patent Application Publication No. 0164209, Published Dec. 11, 1985. IEE Publication "Use of Linearisation and Spectral Techniques in Input and Output Compaction Testing of Digital Networks", by S. L. Hurst, IEE Proceedings E. Computers and Digital Techniques, vol. 136, Part E, No. 1, Jan. 1989, pp. 48-56, Stevenage, Herts., Great Britain.
IBM Technical Disclosure Bulletin, "PRPG/MISR Circuit", pp. 11-13, IBM vol. 32, No. 2, Jul. 1989.
Wang, L. et al., "Circuits for Pseudoexhaustive Test Pattern Generation", IEEE Trans. on Computer-Aided Design, vol. 7, No. 10, Oct. 1988, pp. 1068-1080.
Saluja, K. et al., "A Concurrent Testing Technique for Digital Circuits", IEEE Trans. on Computer-Aided Design, vol. 7, No. 12, Dec. 1988, pp. 1250-1259.
Wang, L. et al., "A Self-Test and Self-Diagnosis Architecture for Boards Using Boundary Scans", Proc. 1st Eur. Test Conf., Paris, Apr. 12-14, 1989, pp. 119-126.
Gloster, C. et al., "Boundary Scan with Built-In Self-Test", IEEE Design & Test of Computers, Feb. 1989, pp. 36-44.
Malleo-Roach John A.
Rutkowski Paul W.
Wu Eleanor
AT&T Bell Laboratories
Baker Stephen M.
Levy Robert B.
LandOfFree
Pseudo-exhaustive self-test technique does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pseudo-exhaustive self-test technique, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pseudo-exhaustive self-test technique will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2153334