Pseudo-dynamic word-line driver

Details Pseudo-dynamic word-line driver Pseudo-dynamic word-line driver

2007-07-10

2007-07-10

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S230060

Reexamination Certificate

active

11290205

ABSTRACT:
In certain embodiments, the present invention is a word-line driver for an address decoder that decodes a multi-bit address to enable access to a row of circuit elements such as memory cells in a block of memory implemented in a dedicated memory device or as part of a larger device, such as an FPGA. The word-line driver has a feed-back latch for each word-line that ensures that the word-line is not energized when that word-line is not selected for access. By controlling the feed-back latch using a decoded address bit value rather than a pre-charged enable signal as do some prior-art dynamic word-line drivers, the word-line driver prevents undesirable energizing of multiple word-lines. The word-line driver can be implemented using less layout area and less power than some analogous prior-art static word-line drivers.

REFERENCES:
patent: 5291076 (1994-03-01), Bridges et al.
patent: 5546024 (1996-08-01), Greenberg

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