Pseudo-concurrent access to a cached shared resource

Details Pseudo-concurrent access to a cached shared resource Pseudo-concurrent access to a cached shared resource

1995-03-23

1997-12-16

Lane, Jack A.

395457, 395473, 395477, 395495, G06F 1200

Patent

active

056995407

ABSTRACT:
A method and apparatus for efficiently controlling the access to a cached shared resource such as dynamic random access memory (DRAM). The access is effected in a pseudo-concurrent manner by two devices such as a central processing unit (CPU) and a bus master agent. While one device accesses data stored in the DRAM, the other device accesses a copy of the DRAM data which is stored in the cache of the shared resource.

REFERENCES:
patent: 4912632 (1990-03-01), Gach et al.
patent: 5129090 (1992-07-01), Bland et al.
patent: 5214775 (1993-05-01), Yabushita et al.
patent: 5291442 (1994-03-01), Emma et al.
patent: 5293491 (1994-03-01), Leung et al.

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