Pruning of short paths in static timing verifier

Details Pruning of short paths in static timing verifier Pruning of short paths in static timing verifier

1997-04-11

2000-04-04

Zimmerman, Brian

Multiplex communications

Diagnostic testing

Path check

370248, 370251, 370252, 370241, 370254, 370256, 364488, 364489, 364490, 364491, 395500, 395550, 395555, G01R 3108, H04L 1228, G06F 1500

Patent

active

060469846

ABSTRACT:
A conservative algorithm for pruning data paths during logic circuit timing verification is disclosed. It uses the correlation between delays on data paths and clock paths in order to prune non-critical data paths during the traversal of the network. Subnetworks are identified in the larger network. Pruning data consisting of the minimum possible delay across all possible paths through the subnetwork, the deskewing clocks, the clock arrival times, and hold times at the synchronizers in the subnetwork are identified the first time each subnetwork is analyzed. In later analysis, the pruning data stored for each subnetwork is used to determine whether a data path can be pruned. A path can be pruned if it is shown to be race-free based on the pruning data. In this way, non-critical paths need only be traced once during timing verification.

REFERENCES:
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patent: 5651012 (1997-07-01), Jones, Jr.
patent: 5657239 (1997-08-01), Grodstein et al.
Ousterhout, J.K., "a switch-Level Timing Verifier for Digital MOS VLSI," IEEE Transactions on Computer-Aided Design, CAD-4(3) :336-349 (Jul. 1985).
Jouppi, N.P., "Timing Analysis and Performance Improvement of MOS VLSI Designs," IEEE Transactions on Computer-Aided Design, CAD6 (4) :650-665 (Jul. 1987).
McWilliams, T.M., "Verification of Timing Constraints on Large Digital Systems," 17th DA Conference, pp. 139-147 (Jun. 1980).

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