Providing serial data clock signal transitions with parity bits

Details Providing serial data clock signal transitions with parity bits Providing serial data clock signal transitions with parity bits

1997-10-10

1999-03-02

Tu, Trinh L.

Excavating

371 377, 39518505, G06F 1100

Patent

active

058780610

ABSTRACT:
A word of data bits is received and a plurality of parity bits for serial transmission of the data bits is generated. The word of data bits and plurality of parity bits are transmitted, wherein the parity bits are generated and transmitted with the data bits, wherein the parity bits are generated in accordance with a parity scheme that ensures that at least one binary transition occurs within each set of n consecutively transmitted bits, wherein n is a specified number. In another embodiment, a serially-transmitted code word comprising a word of data bits and a plurality of parity bits is received, wherein the parity bits are generated by an encoder and transmitted with the data bits, wherein the parity bits are generated in accordance with a parity scheme that ensures that at least one binary transition occurs within each set of n consecutively transmitted bits, wherein n is a specified number. A parity bit syndrome is generated from the code word, and data correction or detection is performed on the code word in accordance with the parity bit syndrome.

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