Providing protection against transistor junction breakdowns...

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Reexamination Certificate

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C365S185180, C365S189090

Reexamination Certificate

active

06781912

ABSTRACT:

BACKGROUND
This invention relates generally to integrated power supply circuitry that is utilized for supplying power in integrated circuits.
Power supply circuitry is typically used to supply power to integrated circuits. One type of power supply circuitry is an integrated supply interface that is often preferred over other circuitry due to size and efficiency. For example, an integrated supply interface may be used to power a chip on an integrated circuit die. The chip circuitry may be implemented using metal oxide (MOS) transistors. However, MOS transistors have voltage limitations that depend on transistor features including gate length, oxide thickness, and doping implants. For example, the drain-substrate PN-junction of a MOS transistor may breakdown, creating a significantly large, and undesirable current through the drain-substrate PN-junction, when a high reverse bias voltage is applied to it. Moreover, the breakdown voltage of the drain-substrate PN-junction is a strong function of the voltage applied to the gate of a MOS transistor, causing the depletion region between the drain and substrate to pinch along the inner drain-substrate junction, underneath the gate. For large values of a drain-to-gate voltage |V
DG
|, the depletion region is pinched sufficiently to further lower the breakdown voltage between the inner drain-substrate PN-junction. This type of breakdown is commonly referred to as gate-aided breakdown of the drain-substrate PN-junction (BVD).
As transistors, such the MOS transistors, are scaled to reduce cost and power, while improving speed, one or more of the transistor features that determine the voltage limitations of MOS transistors may be altered, lowering the supply voltage that may be safely applied. However, many chips, such as flash memory chips use a high voltage power supply (e.g., 12V) to perform memory functions such as program and erase operations, because large electric fields are required to move charge on and off of the floating gate, provide fast program and erase times, and enable backward compatibility with prior products. However, with the lower supply voltage in many fabrication processes deployed to produce memory chips, the gate-aided breakdown voltage has become lower than the desired supply voltage levels (e.g., 12V) for performing memory functions including programming and erasing operations in some flash memories.
Thus, there is a continuing need for better ways to supply power to integrated circuits to protect against transistor junction breakdowns.


REFERENCES:
patent: 6013932 (2000-01-01), Chevallier
patent: 6058456 (2000-05-01), Arimilli et al.
patent: 6112280 (2000-08-01), Shah et al.
patent: RE36932 (2000-10-01), Furutani
patent: 6182194 (2001-01-01), Uemura et al.
patent: 6240027 (2001-05-01), Lee et al.
patent: 2004/0001357 (2004-01-01), Pekny

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