Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2001-06-12
2002-11-12
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S148000, C365S100000
Reexamination Certificate
active
06480438
ABSTRACT:
BACKGROUND
This invention is generally related to programming an array of phase-change memory cells in an integrated circuit device, and is more particularly related to providing equal cell programming conditions for greater uniformity across the array.
Solid state memory devices that use a structural phase-change material as the data storage mechanism (referred to here simply as ‘phase-change memories’) offer significant advantages in both cost and performance over conventional charge storage based memories. In such devices, a phase-change memory array is formed with a number of vertically oriented conductive lines, sometimes called bitlines, and a number of horizontally oriented conductive lines, sometimes called wordlines, arranged in a cross-point matrix. The matrix allows each crossing of a bitline-wordline pair to be associated with a separate memory cell formed nearby in a substrate of the device. To obtain low manufacturing costs in large volumes, every memory cell in the array may be designed to have the same structure. Thus, the cells may be described using only one representative cell, where it is clear that the following description may be applicable to all other cells in the array.
The cell has a small volume of structural phase-change material to store the cell's data. This material may be, for instance, a chalcogenide alloy that exhibits a reversible structural phase-change from amorphous to crystalline. The volume of the phase-change material acts as a programmable resistor and changes from one resistivity state to another, corresponding to a change from one type of structure to another, when the cell has been programmed. The small volume of the material is integrated into a circuit in the cell, perhaps in series with a fixed value matching resistor and an active device such as a transistor switch or a parasitic diode. Such a circuit allows the cell to act as a fast switching programmable resistor. A first terminal of the cell is coupled to the vertically oriented bitline and a second terminal is coupled to the horizontally oriented wordline of the cell's corresponding bitline-wordline pair. The cell is programmed into the desired state by applying a programming pulse to the corresponding bitline-wordline pair, so as to induce a pulse, having a desired voltage, across the cell.
To help reduce manufacturing and operating costs of the array, the same programming pulse may be applied directly to the corresponding bitline-wordline pair of each constituent cell, when seeking to program that cell into the desired state. However, this technique can possibly lead to programming errors in an array that has a large number and greater density of memory cells, because there is a significant amount of variation in cell voltage across such arrays, even though the same programming pulse is applied to the bitline-wordline pairs of replicate cells in the array.
REFERENCES:
patent: 3271591 (1966-09-01), Ovshinsky
patent: 3530441 (1970-09-01), Ovshinsky
patent: 4529896 (1985-07-01), Grandguillot et al.
patent: 6085341 (2000-07-01), Greason et al.
patent: 6141241 (2000-10-01), Ovshinsky et al.
patent: 2001/0047449 (2001-11-01), Wada
Le Thong
Nelms David
Ovonyx Inc.
Trop Pruner & Hu P.C.
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