Protocol for transfer of DMA data

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395325, 364DIG1, 3642684, 3642405, 3642407, 36424231, 36424233, G06F 1328, G06F 1342

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active

051858770

ABSTRACT:
A process for transferring data via DMA between a system resource and a controller via switching logic. During a setup write transaction, the switching logic is set up to enable DMA data to be transferred between a particular system memory and a selected system resource. The setup write transaction also is used to initialize the DMA byte counter. During a subsequent write transaction, DMA pointer registers are initialized with appropriate starting addresses. The controller then transmits a DMA start code and the system resource responds by transmitting an acknowledge code. At that time, DMA data is transmitted between the controller and the system resource via the switching logic.

REFERENCES:
patent: 3665173 (1972-05-01), Bouricius et al.
patent: 3761884 (1973-09-01), Avsan et al.
patent: 3864670 (1975-02-01), Inoue et al.
patent: 3873819 (1975-03-01), Greenwald
patent: 3898621 (1975-08-01), Zelinski et al.
patent: 3961270 (1976-06-01), Ullman et al.
patent: 4012717 (1977-03-01), Censier
patent: 4030074 (1977-06-01), Giorcelli
patent: 4031372 (1977-06-01), Davis
patent: 4075691 (1978-02-01), Davis et al.
patent: 4099234 (1978-07-01), Woods et al.
patent: 4099241 (1978-07-01), Ossfeldt
patent: 4141066 (1979-02-01), Keiles
patent: 4153318 (1979-05-01), Bishop et al.
patent: 4196470 (1980-04-01), Berg
patent: 4200226 (1980-04-01), Piras
patent: 4228496 (1980-10-01), Katzman et al.
patent: 4245344 (1981-01-01), Richter
patent: 4251873 (1981-02-01), Joby
patent: 4253147 (1981-02-01), Macdougall et al.
patent: 4268902 (1981-05-01), Berglund et al.
patent: 4270168 (1981-05-01), Murphy et al.
patent: 4271466 (1981-06-01), Yamamoto et al.
patent: 4271518 (1981-06-01), Birzele et al.
patent: 4298928 (1981-11-01), Etoh et al.
patent: 4313160 (1982-01-01), Kaufman et al.
patent: 4350255 (1982-09-01), Sakata et al.
patent: 4356546 (1982-10-01), Whiteside et al.
patent: 4358823 (1982-11-01), McDonald et al.
patent: 4365293 (1982-12-01), Holtz
patent: 4371754 (1983-02-01), De et al.
patent: 4377843 (1983-03-01), Garringer et al.
patent: 4388683 (1983-06-01), Beifuss et al.
patent: 4400792 (1983-08-01), Strelow
patent: 4403282 (1983-09-01), Holberger et al.
patent: 4418343 (1983-11-01), Ryan et al.
patent: 4424565 (1984-01-01), Larson
patent: 4428044 (1984-01-01), Liron
patent: 4453215 (1984-06-01), Reid
patent: 4455620 (1984-06-01), Watanabe et al.
patent: 4467447 (1984-08-01), Takahashi et al.
patent: 4481572 (1984-11-01), Ochsner
patent: 4486826 (1984-12-01), Wolff et al.
patent: 4495571 (1985-01-01), Staplin, Jr. et al.
patent: 4502117 (1985-02-01), Kihara
patent: 4541094 (1985-09-01), Stiffler
patent: 4569017 (1986-02-01), Renner et al.
patent: 4589066 (1986-05-01), Lam et al.
patent: 4597084 (1986-06-01), Dynneson et al.
patent: 4602327 (1986-07-01), Laviolette et al.
patent: 4610013 (1986-09-01), Long
patent: 4627055 (1986-12-01), Mori et al.
patent: 4631671 (1986-12-01), Kawashita et al.
patent: 4654857 (1987-03-01), Samson et al.
patent: 4688166 (1987-08-01), Schneider
patent: 4692862 (1987-09-01), Cousin et al.
patent: 4700292 (1987-10-01), Campanini
patent: 4751702 (1988-06-01), Beier et al.
patent: 4780809 (1988-10-01), Woffinden et al.
patent: 4821170 (1989-04-01), Bernick et al.
patent: 4837677 (1989-06-01), Burrus, Jr. et al.
patent: 4847750 (1989-07-01), Daniel
patent: 4907228 (1990-03-01), Bruckert et al.
patent: 4916704 (1990-04-01), Bruckert et al.
patent: 4920479 (1990-04-01), Hashiguchi
patent: 5001624 (1991-03-01), Hoffman et al.
M. Euringer et al., "Fault-Tolerant and Fail-Safe Process Control with Redundant Automation Systems," Siemens Power Engineering & Automation VIII, No. 6, Nov./Dec. 1986, pp. 408-410.
"Continuous Processing System Performs Error Checks in Hardware to Eliminate Complex Software," 8167 Computer Design, vol. 21, No. 1, Jan. 1982, pp. 40 and 42.
G. Fazio et al., "A Fault-Tolerant Microcomputer with Fail-Safe Outputs," 8205 Microprocessing & Microprogramming, vol. 12, No. 5, Dec. 1983, pp. 279-284.
T. Krol, "The `(4,2) Concept` Fault-Tolerant Computer," Philips Technical Review, vol. 41, No. 1, 1983/84, pp. 1-11.
W. Eue et al., "SIMIS-C--Die Kompaktversion des Sicheren Mikrocomputersystems SIMIS," 8190 Signal & Draht, vol. 79, No. 4, Apr. 1987, pp. 81-85.
Sequoia Technical Overview Mar. 1985.
Sequoia Hardware Architecture (1984).
Bernstein, Sequoia, Wang Institute of Graduate Studies (date unknown).
"How Technology is Cutting Fault-Tolerance Costs," Electronics 55-58 (Jan. 13, 1986).
Katsuki, et al., "Pluribus-An Operational Fault-Tolerant Multiprocessor," Proceedings of the IEEE vol. 66, No. 10 (Oct. 1978).
Rennels, "Architectures for Fault-Tolerant Spacecraft Computers," Proceedings of the IEEE, vol. 66, No. 10, pp. 1255-1268 (Oct. 1978).
Parallel 300 (1984).
Inselberg, "Multiprocessor Architecture Ensures Fault-Tolerant Transaction Processing," Many MicroSystems (Apr. 1983).
Anita Borg, "Targon/Nixdorf".
Losq, "A Highly Efficient Redundancy Scheme: Self-Purging Redundancy," IEEE Transactions on Computers, vol. C-25, No. 6 (Jun. 1976).
Su, et al., "A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures," IEEE Transactions on Computers, vol. C-29, No. 3, (Mar. 1980).
Takaoka, et al., "N-Fail-Safe Logical Systems," IEEE Transactions on Computers, vol. C-20, No. 5, pp. 536-542 (May 1971).
"System/88 Technical Overview".
Tandem NonStop Computers, Datapro Research Corporation, Computers M11-822-101 to M11-822-119 (Oct. 1986).
Bartlett, "The Tandem Concept of Fault-Tolerance," (view 1985).
Bernstein, "Sequoia: A Fault-Tolerant Tightly-Coupled Computer for Transaction Processing," Technical Report TR-85-03, pp. 1-43 (May 2, 1985).
Datapro Research Corporation Feature Report (Dec. 1985) M07-100-318 to M07-100-323.
The Evolution of Fault-Tolerant Computing, Proceedings of the 1-day symposium on the Evolution of Fault-Tolerant Computing, Ed. by A. Avizienis, H. Kopetz, and J. Laprie (Jun. 30, 1986).
IBM System/88--The Operating System Reference--Jul. 1985.
Harrison, "S/88 Architecture and Design," S/88 Internals, Share 67 (Aug. 12, 1986).
Chester, "Fault-Tolerant Computers Mature," Systems & Software, pp. 117-129 (Mar. 1985).
Depledge, et al., "Fault-Tolerant Microcomputer Systems for Aircraft," IEEE Conference Proceedings 36, 1977, Proc. Conf. on Computer Systems & Technology Engineering, pp. 205-220 (Mar. 1977).
Beck, et al., "Implementation Issues in Clock Synchronization," Mar. 15, 1986 Draft.

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