Protocol and system for performing line-fill address during copy

Details Protocol and system for performing line-fill address during copy Protocol and system for performing line-fill address during copy

1995-02-10

1997-11-11

Swann, Tod R.

395445, G06F 1200

Patent

active

056873506

ABSTRACT:
A protocol and system for providing a next read address during an address phase of a write transaction in a data cache unit in a processing unit is disclosed. The processing unit includes the data cache unit and an instruction cache unit both coupled to an address bus and a data bus, respectively. The two buses are further connected to a system memory controller separate from the microprocessor. The protocol and system provide for next read address and a next transaction during the address phase in a current write transaction. The protocol loads a pre-fetched address within a current data transaction and then generates a next line fill address using the pre-fetched address which is concatenated to the current data transaction. The pre-fetched address is used to generate a next line fill address. The line fill address is generated upon determining if a cache read miss has occurred and if so, copying a modified cache line back to the main system memory and then loading the missed cache read line into the internal cache from the system memory controller.

REFERENCES:
patent: 4084231 (1978-04-01), Capozzi et al.
patent: 4884197 (1989-11-01), Sachs et al.
patent: 5148536 (1992-09-01), Witek
patent: 5226130 (1993-07-01), Favor
patent: 5247642 (1993-09-01), Kadlec et al.
patent: 5247643 (1993-09-01), Shottan
patent: 5275216 (1994-01-01), Moyer et al.
patent: 5353426 (1994-10-01), Patel
patent: 5353429 (1994-10-01), Fitch
patent: 5355467 (1994-10-01), MacWilliams et al.
patent: 5471602 (1995-11-01), DeLano
patent: 5499355 (1996-03-01), Krishnamohan
The Cache Memory Book, Jim Handy (c) 1993 ISBN: 0-12-322985-5.
IBM Technical Disclosure Bulletin, vol. 35, No. 6, Nov. 1992, "Interoperability Between MVS and Posix Functions".
IBM Technical Disclosure Bulletin, vol. 37, No. 06A, Jun. 1994, "Memory Queue Priority Mechanism for a Risc Processor".

Affiliated with

Also associated with

Rating

Protocol and system for performing line-fill address during copy does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Protocol and system for performing line-fill address during copy, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Protocol and system for performing line-fill address during copy will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1236667