Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Patent
1998-12-11
2000-10-24
Coleman, Eric
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
712 31, G06F 922
Patent
active
061382280
ABSTRACT:
A protocol and internal link system of a micro-controller in which components, interconnected by a parallel BUS link, exchange during a transaction successive messages on a plurality of clock cycles. A master transmitting component transmits, on a current clock cycle, to an addressee slave receiver component, an instruction message, encoded on N+p bits, and comprising a main field, N bits, and an auxiliary field, p bits, comprising an operation code, a signature identifying master and slave component and their transaction. A proof of transmission message and an acknowledgement message are transmitted from the master component to the slave component and vice versa on the following clock cycle. These steps are repeated on at least one subsequent clock cycle.
REFERENCES:
patent: 4961140 (1990-10-01), Pechanek
patent: 5235683 (1993-08-01), Dahlerud
patent: 5854939 (1998-12-01), Wallan
patent: 6032178 (2000-02-01), Baciogalupo
patent: 6061749 (2000-05-01), Webb
Coleman Eric
T.Sqware Inc.
LandOfFree
Protocol and bus link system between components of a micro-contr does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Protocol and bus link system between components of a micro-contr, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Protocol and bus link system between components of a micro-contr will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1975882