Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1998-09-10
2000-11-07
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438424, 438427, 148DIG50, H01L 2176
Patent
active
061436259
ABSTRACT:
An isolation trench (60) may comprise a trench (20) formed in a semiconductor layer (12). A barrier layer (22) may be formed along the trench (20). A protective liner (50) may be formed over the barrier layer (22). The protective liner (50) may comprise a chemically deposited oxide. A high density layer of insulation material (55) may be formed in the trench (20) over the protective liner (50).
REFERENCES:
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patent: 5561078 (1996-10-01), Tasaka
patent: 5719085 (1998-02-01), Moon et al.
patent: 5736462 (1998-04-01), Takahashi et al.
patent: 5741740 (1998-04-01), Jang et al.
patent: 5976947 (1999-11-01), Reinberg
U.S. application No. 08/871,738, filed Jun. 9, 1997, entitled "Integrated Circuit Insulator and Method", by Somnath S. Nag et al. (pending).
Chatterjee Amitava
Chen Ih-Chin
Nag Somnath S.
Bassuk Lawrence J.
Dang Trung
Telecky Frederick J.
Texas Instruments Incorporated
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