Protective layers for MRAM devices

Details Protective layers for MRAM devices Protective layers for MRAM devices

2002-04-30

2004-08-31

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S238000, C438S381000

Reexamination Certificate

active

06783995

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is directed generally to magnetic memory devices for storing digital information and, more particularly, to methods and structures for forming electrical contacts to the devices.
2. Description of the Related Art
The digital memory most commonly used in computers and computer system components is the dynamic random access memory (DRAM), wherein voltage stored in capacitors represents digital bits of information. Electric power must be supplied to these memories to maintain the information because, without frequent refresh cycles, the stored charge in the capacitors dissipates, and the information is lost. Memories that require constant power are known as volatile memories.
Non-volatile memories do not need refresh cycles to preserve their stored information, so they consume less power than volatile memories and can operate in an environment where the power is not always on. There are many applications where non-volatile memories are preferred or required, such as in cell phones or in control systems of automobiles.
Magnetic random access memories (MRAMs) are non-volatile memories. Digital bits of information are stored as alternative directions of magnetization in a magnetic storage element or cell. The storage elements may be simple, thin ferromagnetic films or more complex layered magnetic thin-film structures, such as tunneling magnetoresistance (TMR) or giant magnetoresistance (GMR) elements.
Memory array structures are formed generally of a first set of parallel conductive lines covered by an insulating layer, over which lies a second set of parallel conductive lines, perpendicular to the first lines. Either of these sets of conductive lines can be the bit lines and the other the word lines. In the simplest configuration, the magnetic storage cells are sandwiched between the bit lines and the word lines at their intersections. More complicated structures with transistor or diode latching can also be used. When current flows through a bit line or a word line, it generates a magnetic field around the line. The arrays are designed so that each conductive line supplies only part of the field needed to reverse the magnetization of the storage cells. In one arrangement, switching occurs only at those intersections where both word and bit lines are carrying current. Neither line by itself can switch a bit; only those cells addressed by both bit and word lines can be switched.
The magnetic memory array of
FIG. 1
illustrates, in a basic way, the three functional layers of a TMR device. TMR devices
10
work by electron tunneling from one magnetic layer to another through a thin barrier layer
12
. The tunneling probability is greatest when the magnetic layers
14
,
16
, on either side of the barrier layer
12
, have parallel magnetizations and least when the magnetizations are anti-parallel. In order for the devices to function properly, these layers must be electrically isolated from one another. Any short circuiting of the layers bypasses the data storage of the device.
Copper conductors for MRAM arrays are currently preferred in order to reduce the likelihood of problems with electromigration caused by the high current density carried by the bit and word lines. Copper conducting lines are usually made using a damascene process. In
FIG. 1
, the copper conducting line
18
, in contact with the bottom of the TMR devices
10
, is shown in the plane of the paper. To make conducting lines over the devices, first a thick insulating layer is deposited over the MRAM array. Trenches are etched into the insulating layer to expose the top surfaces of the TMR devices
10
. Copper is deposited to fill the trenches and make electrical contact to the TMR devices
10
. Top electrodes (not shown in
FIG. 1
) over the TMR devices
10
are preferably also formed by damascene processing.
Although trenches are usually etched anisotropically through a patterned mask, overetching can occur both in the width of the trench and in the depth of the etch. If the etch is too deep, gaps develop along the sidewalls of the memory devices. Subsequent copper deposition fills the gaps and can short the memory devices. A more robust method of forming conducting lines over magnetic memory devices is needed.
SUMMARY OF THE INVENTION
A method of forming a magnetic random access memory (MRAM) is provided. A plurality of individual magnetic memory devices with cap layers are defined on a substrate. A continuous first insulator layer is provided over the substrate and the magnetic memory devices. Portions of the first insulator layer are removed at least over the magnetic memory devices and then the cap layers are selectively removed, thus exposing active top surfaces of the magnetic memory devices. Top conductors are formed in contact with the active top surfaces of the magnetic memory devices.
In accordance with another aspect of the invention, a method for forming a magnetoresistive memory on a semiconductor substrate having an underlying integrated circuit component is provided. A plurality of protrusions comprising magnetoresistive memory layers with a capping layer as an uppermost layer is formed. A conformal layer of spacer material is deposited over the protrusions and a spacer etch is performed, thereby forming spacers along side surfaces of the protrusions. A layer of insulating material is formed over the protrusions, the spacers and the substrate. The insulating material is removed at least over the protrusions, the capping layer is selectively etched away and a metallization process is performed to make contact to the magnetoresistive memory layers.
In another aspect of the invention, a magnetic memory structure is provided. The structure comprises a plurality of magnetic memory stacks, each stack in a stud configuration. There is a first insulator layer around the magnetic memory stacks, and the top surfaces of the magnetic memory stacks are recessed below the top surface of the first insulator layer. There is a metal conductor in contact with the top surface of the magnetic memory stacks.


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