Protective interleaf for stacked wafer shipping

Details Protective interleaf for stacked wafer shipping Protective interleaf for stacked wafer shipping

2006-11-21

2006-11-21

Coleman, W. David (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Miscellaneous

C257SE25031, C053S255000

Reexamination Certificate

active

07138726

ABSTRACT:
A package includes a first and a second wafer stored therein in a stacked configuration. The first wafer has interconnection conductor material portions extending from a first surface thereof. The interconnection conductor material portions have a maximum height. An interleaf member is located between the first and second wafers. A first recessed portion is formed in the interleaf member, and it has an outer perimeter shape corresponding to an outer perimeter shape of the first wafer. The first recessed portion has a first depth from a top surface of the interleaf member. A second recessed portion is formed in the interleaf member and located at least partially within the first recessed portion, and it has a bottom surface at a second depth from the top surface. The second depth is greater than the first depth. The second depth minus the first depth is greater than the maximum height.

REFERENCES:
patent: 4787508 (1988-11-01), Wu et al.
patent: 4792044 (1988-12-01), Nishizawa et al.
patent: 5699916 (1997-12-01), Liang
patent: 6533123 (2003-03-01), Nakamura et al.

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