Protective device for a semiconductor integrated circuit includi

Details Protective device for a semiconductor integrated circuit includi Protective device for a semiconductor integrated circuit includi

1982-06-28

1985-09-10

Clawson, Jr., Joseph E.

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

357 2313, 357 41, 357 59, 361 56, 361 91, H01L 2702

Patent

active

045410020

ABSTRACT:
A protective device for protecting a semiconductor integrated circuit from the destruction phenomenon which occurs due to an extremely high input voltage. The protective device comprises a protective input MIS transistor having a semiconductor substrate, a diffusion region formed in the semiconductor substrate, and an input electrode wiring layer electrically connected to the diffusion region. The input electrode wiring layer does not directly contact the diffusion region, rather, it contacts the diffusion region through a first polysilicon layer and a second polysilicon layer. The first polysilicon layer is formed on an insulating film adjacent to the diffusion region, and the second polysilicon layer is formed so as to be in contact with the first polysilicon layer and the diffusion region. The concentration of impurities in the first polysilicon layer is higher than that in the second polysilicon layer.

REFERENCES:
patent: 4244000 (1981-01-01), Ueda et al.
patent: 4270137 (1981-05-01), Coe
patent: 4352997 (1982-10-01), Raymond et al.
IBM Technical Disclosure Bulletin, "Protect Device for LSI Fet Circuits", by N. Edwards, vol. 22, No. 6, Nov. 1979, p. 2326.
IBM Technical Disclosure Bulletin, "Resistor-Thick Oxide FET Gate Protection Device for Thin Oxide FET", by W. Fischer, vol. 13, No. 5, Oct. 1970, pp. 1272-1273.
Patents Abstracts of Japan, vol. 3, No. 10, Jan. 29, 1979, p. 93, #53-138,679.
16th Annual Proceedings on Reliability Physics, "VMOS Electrostatic Protection", by I. S. Bhatti et al., Apr. 1978, pp. 140-145.
IEEE Transactions on Electron Devices, "A Novel MOS PROM using a Highly Resistive Poly-Si Resistor", by M. Tanimoto et al., vol. ED-27, No. 3, Mar. 1980.

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