Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
2000-02-22
2003-02-04
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S649000, C257S760000, C257S900000
Reexamination Certificate
active
06515350
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a method for depositing protective spacer layers on stacked arrays, e.g. gate stacks, in a semiconductor device, and more specifically, to a method of deposition of spacer layers which results in enhanced resistance to contact erosion, improved conformality and cross wafer uniformity, and better chemical utilization. The invention also relates to the stacked arrays having the improved protective spacer layers deposited thereon.
BACKGROUND OF THE INVENTION
Silicon nitride (Si
3
N
4
) protective layers are commonly used as spacer material in semiconductor wafer fabrication. These spacer layers protect the stacked structures, e.g. “gate stacks”, located on the wafers during a self-aligned contact etching (SAC) process. Shown in
FIG. 1A
is a portion of a semiconductor wafer
10
including substrate
12
formed of a semiconductor material such as silicon having field oxide regions
17
and doped regions
19
. Gate stacks
14
, formed of at least an oxide layer
21
and an overlying conductive layer
23
, e.g. doped polysilicon, are fabricated on substrate
12
and are spaced apart from one another. Overlying the gate stacks is a protective silicon nitride layer
16
. An insulative layer
18
, in turn, overlays the array of gate stacks
14
and the silicon nitride layer
16
. The insulative layer
18
may be formed of a material such as Boro-Phospho-Silicate Glass (BPSG). The illustrated structure may be used, for example, as an intermediate structure in DRAM memory cell fabrication.
Unfortunately, silicon nitride is not an ideal spacer film material. As shown in
FIGS. 1B and 1C
, often times contact erosion occurs at the side interface of the protective silicon nitride layer
16
and the gate stack(s)
14
during a self-aligned contact (SAC) etching process
20
. As shown in
FIG. 1C
, the etching chemistry/conditions utilized in the SAC process may erode the silicon nitride layer
16
leaving crevices or cracks
22
at this interface which exposes the sides of the gate stacks
14
. As shown in
FIG. 1D
, the seepage residue and deterioration of the silicon nitride layer
16
interferes with the performance of a fabricated conductive plug
24
, e.g. a polysilicon plug, which needs to be isolated from the gate conductive layer
23
.
Erosion of the silicon nitride layer during SAC etching can be considerably mitigated by utilizing bistertbutylaminosilane (BTBAS) as a precursor material. The BTBAS reacts with ammonia (NH
3
) to form the silicon nitride layer
16
. However, this BTBAS-derived silicon nitride layer in practice is difficult to form uniformly across a wafer as a result of gas transport effects when the layer is formed in a batch furnace. This problem of nonuniform deposition of the silicon nitride layer across the gate stack array areas and extending to the open areas of the wafer has meant that the sides of the gate stacks often receive only about 70% of the total material which is received in the open areas. In addition, while the BTBAS deposited silicon nitride layer exhibits profile conformality up to 85% (from the open areas to the sides of the gate stack arrays), higher conformality (approaching 100%) is often desired in some applications. Further, the cost associated with using precursors such as BTBAS requires that chemical utilization of the compound(s) involved in forming the spacer film layers be increased to provide lower cost processing.
What is therefore needed in the art is an improved method of spacer film layer deposition which results in improved conformality and uniformity, as well as better chemical utilization of all compounds involved in the deposition process across all segments of the semiconductor wafer. Also needed are gate stacks with improved contact erosion resistivity.
SUMMARY OF THE INVENTION
The invention provides a method for protecting a gate stack in an integrated circuit wafer which comprises depositing a thin seed or nucleation layer of silicon nitride on the gate stack, and thereafter depositing a primary layer of silicon nitride using bistertbutylaminosilane (BTBAS) as a precursor, either alone or combination with other materials. The nucleation and primary layers form a spacer film having improved uniformity and conformality, and obtain a better chemical utilization of the BTBAS.
The invention further provides a semiconductor device containing a gate stack that has a nucleation layer of silicon nitride formed on the sides and top thereof, and over the nucleation layer, a primary layer containing more silicon nitride, alone or in combination with other materials, which is deposited using BTBAS as a precursor. Together the nucleation and primary layers form a spacer film which will protect a gate stack array of a semiconductor device from the corrosive effects of the chemicals, e.g. freon-containing compounds, used in dry contact opening SAC etching. The spacer film herein provided will also exhibit a reduced etchant rate in many types of fluorine-based, wet etchant chemicals, such as hydrofluoric acid (HF) and HF/TMAH.
In addition, the invention provides an integrated circuit having a substrate with at least one gate stack thereon. A spacer film is formed over the gate stack and contains a nucleation layer, and over the nucleation layer, a primary layer of silicon nitride. A conductive plug is provided in an insulation layer in the circuit, and is in contact with the substrate. The conductive plug is separated from the gate stack by the spacer film.
Additional advantages and features of the present invention will become more readily apparent from the following detailed description and drawings which illustrate various embodiments of the invention.
REFERENCES:
patent: 4636822 (1987-01-01), Codella et al.
patent: 5168072 (1992-12-01), Moslehi
patent: 5719425 (1998-02-01), Akram et al.
patent: 6091121 (2000-07-01), Oda
patent: 6130102 (2000-10-01), White, Jr. et al.
patent: 6144071 (2000-11-01), Gardner et al.
patent: 6162737 (2000-12-01), Weimer et al.
patent: 6261891 (2001-07-01), Cheng et al.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Thomas Tom
Tran Thien F.
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