1988-07-28
1989-12-26
James, Andrew J.
357 2313, 357 231, H01L 2978
Patent
active
048901431
ABSTRACT:
A self-protected MOS gated device includes a PN junction disposed in an electrical path between the source electrode and the gate contact of the device and integrally formed with a DMOS cell of the device to protect the DMOS cell from surge voltages. The PN junction has conductivity characteristics selected to provide junction breakdown at a predetermined voltage level and at a predetermined location along the junction.
REFERENCES:
patent: 3555374 (1971-01-01), Usuda
patent: 3667009 (1972-05-01), Rugg
patent: 3673428 (1972-06-01), Athanas
patent: 3712995 (1973-01-01), Steudel
patent: 3748547 (1973-06-01), Sugimoto
patent: 3754171 (1973-08-01), Anzai et al.
patent: 3764864 (1973-10-01), Okumura et al.
patent: 3806773 (1974-04-01), Watanabe
patent: 4110775 (1978-08-01), Festa
patent: 4492974 (1985-01-01), Yoshida et al.
patent: 4580063 (1986-04-01), Torelli et al.
patent: 4617482 (1986-10-01), Matsuda
patent: 4656491 (1987-04-01), Igaraski
Baliga Bantval J.
Korman Charles S.
Davis Jr. James C.
General Electric Company
James Andrew J.
Snyder Marvin
Soltz David
LandOfFree
Protective clamp for MOS gated devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Protective clamp for MOS gated devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Protective clamp for MOS gated devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1579585