Protective circuit for memory devices

Details Protective circuit for memory devices Protective circuit for memory devices

1986-03-27

1989-01-17

Shaw, Gareth D.

Boots, shoes, and leggings

307 66, 365229, G06F 1216

Patent

active

047991852

ABSTRACT:
A circuit for protecting the contents of memory devices, each having a power supply voltage input terminal and a disabling signal input terminal following a failure in an A.C.-derived D.C. potential in which respective time delay circuits couple battery potential to said power supply voltage terminals and to said disabling signal input terminals at respective predetermined times after said failure.

REFERENCES:
patent: 4096560 (1978-06-01), Footh
patent: 4122359 (1978-10-01), Breikss
patent: 4130899 (1978-12-01), Bowman et al.
patent: 4234920 (1980-11-01), Van Ness et al.
patent: 4290116 (1981-10-01), Morse
patent: 4327298 (1982-04-01), Burgin
patent: 4366481 (1982-12-01), Main et al.
patent: 4375663 (1983-03-01), Arcara et al.
patent: 4451742 (1984-05-01), Aswell
patent: 4492876 (1985-01-01), Colbert et al.
patent: 4531214 (1985-07-01), Torres et al.
patent: 4563628 (1986-01-01), Tietz et al.

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