Protective circuit for a power field-effect transistor

Details Protective circuit for a power field-effect transistor Protective circuit for a power field-effect transistor

1999-10-04

2002-07-30

Sircus, Brian (Department: 2839)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific quantity comparison means

C307S010700

Reexamination Certificate

active

06426857

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a protective circuit for a field-effect transistor (FET) operated as a power switch whose drain-, source- and gate-terminal are controllable.
BACKGROUND INFORMATION
In order to reduce the power dissipation in semiconductor switches, field-effect transistors, for example MOSFETs, are used; in the ON (conductive) state, these exhibit a very low resistance between source and drain. In this way it is possible to reduce measures for cooling the semiconductor switch to a minimum or omit them altogether. Thus, for example, the power dissipation can be reduced to 0.5 W for a resistance of 5 m&OHgr; and a load current I
Load
of 10 A.
In the OFF or, respectively, ON state of the semiconductor switch, in the case of a FET, the parasitic inverse diode acting between drain and source forms a current path if the power supply voltage is connected with incorrect polarity.
If load current I
Load
is limited to 10 A by load resistance R
Load
and the voltage drop across the inverse diode is 0.8 V (diode-dependent), the power dissipation increases to 8 W. This power dissipation can lead to the destruction of the FET unless there are cooling measures (e.g., heat sinks).
It is an object of the present invention to provide a protective circuit for a field-effect transistor (FET), which reliably prevents an increase in the power dissipation even when the power supply voltage has the incorrect polarity.
SUMMARY OF THE INVENTION
According to the present invention, this object is achieved in that the switching voltage is suppliable to the gate as a driving voltage via a charge pump; that the charge pump is powered via a bridge circuit independently of the polarity of the applied power supply voltage; and that, in case of incorrect polarity of the power supply voltage, the charge pump is driven to output a driving voltage via a diode connected to the base (GND).
With this protective circuit, in case of incorrect polarity of the power supply voltage, the FET is driven by the additional driving circuit via the diode and the charge pump, so that the path between the drain and the source becomes a low-resistance path. The parasitic inverse diode is practically short-circuited, and thus the power dissipation is reduced to the value corresponding to correct connection of the FET. A heat sink can therefore be dispensed with, or the measures for cooling the FET can be correspondingly reduced. Destruction of the FET is reliably prevented.
For the dual driving of the charge pump, the charge pump exhibits a control input to which the switching voltage is suppliable, and which is connected via the diode to the base, the diode being ON in case of a power supply voltage applied to the base (i.e., in case of interchanged polarity). In normal operation, the switching voltage is applied to the control input of the charge pump, while in case of incorrectly polarized power supply voltage, the control input of the charge pump is driven via the diode between base and control input by the power supply voltage incorrectly applied to the base.
The protective circuit is universally applicable if care is taken that the FET is made as an n-channel or p-channel MOSFET, the polarities of the power supply voltage, the switching voltage and the driving voltage being correspondingly interchanged and the diode being connected in the designated forward direction between the base and the control input of the charge pump.
The switching effort can be held low by using, as the charge pump, a commercial integrated circuit whose input signal and output signal are adapted to the polarity of the switching voltage. The present invention is described in greater detail on the basis of an exemplary embodiment of an n-channel MOSFET illustrated as a circuit diagram.


REFERENCES:
patent: 4775959 (1988-10-01), Sato et al.
patent: 5517379 (1996-05-01), Williams
patent: 5539610 (1996-07-01), Williams
patent: 5610793 (1997-03-01), Luu
patent: 5936317 (1999-08-01), Sasanouchi et al.
patent: 6061445 (2000-05-01), Rahamim et al.
patent: 374 1394 (1989-06-01), None
patent: 4139378 (1993-06-01), None
patent: 195 34159 (1997-03-01), None
IBM, Reverse Bias Over-current projection for Power Field-Effect Transistor, Jul. 1, 1986, IBM Technical Disclosure Bulletin vol. 29, pp. 567-569.

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