Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Patent
1996-07-12
1998-04-14
Gaffin, Jeffrey A.
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
361111, 257355, H02H 900
Patent
active
057399980
ABSTRACT:
A protective circuit in a semiconductor integrated circuit for protecting a semiconductor integrated circuit chip from an over voltage having a predetermined voltage potential level supplied to an input/output terminal in the semiconductor integrated circuit having a P-MOS FET whose drain electrode is connected to the input/output terminal and whose source electrode and drain electrode are commonly connected to a first power source, and a first N-MOS FET whose source electrode is connected to a back gate of the P-MOS FET, whose drain electrode and gate electrode are connected to the first power source and whose back gate is connected to a second power source, and a second N-MOS FET whose drain electrode is connected to the input/output terminal and whose source electrode, gate electrode and whose back gate are connected to the second power source.
REFERENCES:
patent: 4858055 (1989-08-01), Okitaka
patent: 4868705 (1989-09-01), Shiochi et al.
patent: 5086365 (1992-02-01), Lien
patent: 5514893 (1996-05-01), Miyanaga et al.
patent: 5615073 (1997-03-01), Fried et al.
Gaffin Jeffrey A.
Kabushiki Kaisha Toshiba
Sherry Michael J.
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