Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Patent
1998-09-25
2000-07-18
Sherry, Michael J.
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
361 58, 361111, 361 912, H02H 322
Patent
active
060915927
ABSTRACT:
A protective circuit for protecting a circuit from a destructive voltage or current, comprising a MIS transistor, and at least one resistor connected in series with the MIS transistor for limiting current flow through the MIS transistor, wherein a resistance value R of the at least one resistor connected in series with the MIS transistor satisfies the relation R>(A-B)/C, wherein A is a surge voltage against which protection is provided, B is a hold voltage at a breakdown of the MIS transistor, and C is a maximum allowable current of the MIS transistor. The at least one resistor is connected in series with a source of the MIS transistor, a drain of the MIS transistor, or both the source and the drain of the MIS transistor, and the resistance value of the resistance is preferably smallest value that satisfies the relation R>(A -B)/C.
REFERENCES:
patent: 4456939 (1984-06-01), Ozaki et al.
patent: 4527213 (1985-07-01), Ariizumi
patent: 5430602 (1995-07-01), Chin et al.
patent: 5760630 (1998-06-01), Okamoto
Seiko Instruments Inc.
Sherry Michael J.
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