Protection system for CMOS integrated circuits

Details Protection system for CMOS integrated circuits Protection system for CMOS integrated circuits

1987-05-15

1989-04-04

Carroll, J.

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

357 40, 357 42, 357 43, 357 44, 357 45, 357 51, 357 88, 361 56, 361 58, 361 91, H01L 2978, H01L 2702, H01L 2710

Patent

active

048190470

ABSTRACT:
A protection system for CMOS integrated circuits to prevent inadvertent damage caused by electrostatic discharge includes a low impedance power supply bus structure and a plurality of bipolar and MOS clamping networks. The bipolar clamping networks are formed around each of the bonding pads for interlinking all of them together through the low impendance power supply bus structure. When any one of the bonding pads receives a higher voltage than a predetermined value and another remaining one of the bonding pads contacts a ground potential, current is routed from the one bonding pad through the low impedance power supply bus structure to the other bonding pad in order to discharge the same.

REFERENCES:
patent: 4412237 (1983-10-01), Maksumura et al.
patent: 4453174 (1984-06-01), Kawasaki et al.
patent: 4476476 (1984-10-01), Yu et al.
patent: 4654689 (1987-03-01), Fujii
patent: 4661815 (1987-04-01), Takayama et al.

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