Protection structure against latch-up in a CMOS circuit

Details Protection structure against latch-up in a CMOS circuit Protection structure against latch-up in a CMOS circuit

1992-06-03

1994-09-13

Wambach, Margaret Rose

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307566, 307567, 307318, 361 91, 361111, H01P 122, H03K 326

Patent

active

053471857

ABSTRACT:
A CMOS circuit protected against latch-up. A limiter parallel to the internal circuitry of the CMOS circuit increases the external current for the triggering of the latch-up in the event of overvoltage on the supply. In one embodiment, the parallel limiter is intrinsically protected against electrostatic discharges. In another embodiment, the limiter is protected by a series connected resistor and a separate shunt-connected ESD protection structure.

REFERENCES:
patent: 4032800 (1977-06-01), Droschen et al.
patent: 4922367 (1990-05-01), Hidaka
patent: 4939616 (1990-07-01), Roundtree
patent: 4948989 (1990-08-01), Spratt
patent: 5006736 (1991-04-01), Davies
patent: 5196981 (1993-03-01), Kuo
patent: 5198957 (1993-03-01), Welty et al.
Patent Abtracts of Japan, vol. 11, No. 165 (E-510)(2612) May 27, 1987 (summarizing Japanese app'n JP-A-61,296,770).
Patent Abstracts of Japan, vol. 11, No. 265 (E-535)(2712) Aug. 27, 1987 (summarizing Japanese app'n JP-A-62,069,661).

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