Protection of tungsten alignment mark for FeRAM processing

Details Protection of tungsten alignment mark for FeRAM processing Protection of tungsten alignment mark for FeRAM processing

2002-03-13

2003-03-04

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C438S677000

Reexamination Certificate

active

06528386

ABSTRACT:

CROSS-REFERENCE TO RELATED PATENT/PATENT APPLICATIONS
The following patents/patent applications are hereby incorporated herein by reference:
Patent No./Ser. No.
Filing Date
TI Case No.
09/739,065
Dec. 18, 2000
TI-29966
09/741,650
Dec. 19, 2000
TI-29968
09/741,479
Dec. 19, 2000
TI-29969
09/741,675
Dec. 19, 2000
TI-29972
09/741,677
Dec. 19, 2000
TI-30077
09/741,688
Dec. 19, 2000
Ti-30137
09/392,988
Sep. 09, 1999
TI-26586
09/105,738
Jun. 26, 1998
TI-25297
09/238,211
Jan. 27, 1999
TI-26778
FIELD OF THE INVENTION
The instant invention pertains to semiconductor device fabrication and processing and more specifically to a method of fabricating a ferroelectric memory device.
BACKGROUND OF THE INVENTION
Several trends exist presently in the semiconductor device fabrication industry and the electronics industry. Devices are continuously getting smaller and requiring less power. A reason for these trends is that more personal devices are being fabricated which are relatively small and portable, thereby relying on a small battery as its primary supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a computational device which has memory and logic functions integrated onto the same semiconductor chip. Preferably, this memory will be configured such that if the battery dies, the contents of the memory will be retained. Such a memory device which retains its contents while power is not continuously applied thereto is called a non-volatile memory. Examples of conventional non-volatile memory include: electrically erasable, programmable read only memory (“EEPPROM”) and FLASH EEPROM.
A ferroelectric memory (FeRAM) is a non-volatile memory which utilizes a ferroelectric material, such as strontium bismuth tantalate (SBT) or lead zirconate titanate (PZT), as a capacitor dielectric situated between a bottom electrode and a top electrode. Both read and write operations are performed for an FeRAM. The memory size and memory architecture affects the read and write access times of an FeRAM. Table 1 illustrates exemplary differences between different memory types.
TABLE 1
FeRAM
Property
SRAM
Flash
DRAM
(Demo)
Voltage
>0.5 V
Read >0.5 V
>1 V
3.3 V
Write (12 V)
(±6 V)
Special Transistors
NO
YES
YES
NO
(High
(Low
Voltage)
Leakage)
Write Time
<10 ns
100 ms
<30 ns
60 ns
Write Endurance
>10
15
<10
5
>10
15
>10
13
Read Time (single/
<10 ns
<30 ns
<30 ns/<2
60 ns
multi bit)
ns
Read Endurance
>10
15
>10
15
>10
15
>10
13
Added Mask for
0
~6-8
~6-8
~3
embedded
Cell Size (F~metal
~80 F
2
~8 F
2
~8 F
2
~18 F
2
pitch/2)
Architecture
NDRO
NDRO
DRO
DRO
Non volatile
NO
YES
NO
YES
Storage
I
Q
Q
P
The non-volatility of an FeRAM is due to the bistable characteristic of the ferroelectric memory cell. An FeRAM cell may be selected by two concurrent X and Y voltage pulses, respectively, wherein X and Y correspond to a specific bit line and word line, respectively, identified by horizontal and vertical decoder circuitry. The FeRAM cells of the capacitor array which receive only one voltage pulse remain unselected while the cell that receives both an X and Y voltage signal flips to its opposite polarization state or remains unchanged, depending upon its initial polarization state, for example.
Two types of ferroelectric memory cells are used commonly, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell (referred to as a 1T/1C or 1C memory cell) requires less silicon area (thereby increasing the potential density of the memory array), but is less immune to noise and process variations. Additionally, a 1C cell requires a voltage reference for determining a stored memory state. The dual capacitor memory cell (referred to as a 2T/2C or 2C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2C memory cell is more stable than a 1C memory cell.
As illustrated in prior art
FIG. 1
, a 1T/1C FeRAM cell
10
includes one transistor
12
and one ferroelectric storage capacitor
14
. A bottom electrode of the storage capacitor
14
is connected to a drain terminal
15
of the transistor
12
. The 1T/1C cell
10
is read from by applying a signal to the gate
16
of the transistor (word line WL)(e.g., the Y signal), thereby connecting the bottom electrode of the capacitor
14
to the source of the transistor (the bit line BL)
18
. A pulse signal is then applied to the top electrode contact (the plate line or drive line DL)
20
. The potential on the bitline
18
of the transistor
12
is, therefore, the capacitor charge divided by the bitline capacitance. Since the capacitor charge is dependent upon the bistable polarization state of the ferroelectric material, the bitline potential can have two distinct values. A sense amplifier (not shown) is connected to the bitline
18
and detects the voltage associated with a logic value of either 1 or 0. Frequently the sense amplifier reference voltage is a ferroelectric or non-ferroelectric capacitor connected to another bitline that is not being read. In this manner, the memory cell data is retrieved.
A characteristic of a ferroelectric memory is that a read operation is destructive in some applications. The data in a memory cell is then rewritten back to the memory cell after the read operation is completed. If the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite (onto that cell) the correct polarization value as the bit just read from the cell. This is similar to the operation of a DRAM. If the drive line voltage was small enough not to switch the ferroelectric then the read operation was not destructive. In general, a non-destructive read requires a much larger capacitor than a destructive read and, therefore, requires a larger cell size.
As illustrated, for example, in prior art
FIG. 2
, a 2T/2C memory cell
30
in a memory array couples to a bit line (“bitline”)
32
and an inverse of the bit line (“bitline-bar”)
34
that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The dual capacitor ferroelectric memory cell comprises two transistors
36
and
38
and two ferroelectric capacitors
40
and
42
, respectively. The first transistor
36
couples between the bitline
32
and a first capacitor
40
, and the second transistor
38
couples between the bitline-bar
34
and the second capacitor
42
. The first and second capacitors
40
and
42
have a common terminal or plate (the drive line DL)
44
to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors
36
and
38
of the dual capacitor ferroelectric memory cell
30
are enabled (e.g., via their respective word line
46
) to couple the capacitors
40
and
42
to the complementary logic levels on the bitline
32
and the bitline-bar line
34
corresponding to a logic state to be stored in memory. The common terminal
44
of the capacitors is pulsed during a write operation to polarize the dual capacitor memory cell
30
to one of the two logic states.
In a read operation, the first and second transistors
36
and
38
of the dual capacitor memory cell
30
are enabled via the word line
46
to couple the information stored on the first and second capacitors
40
and
42
to the bar
32
and the bitline-bar line
34
, respectively. A differential signal (not shown) is thus generated across the bitline
32
and the bar-bar line
34
by the dual capacitor memory cell
30
. The differential signal is sensed by a sense amplifier (not shown) which provides a signal corresponding to the logic level stored in memory.
A memor

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