Protection of proprietary circuit designs during gate level stat

Details Protection of proprietary circuit designs during gate level stat Protection of proprietary circuit designs during gate level stat

1996-09-25

1999-03-23

Teska, Kevin J.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

058869000

ABSTRACT:
A method for providing a nonfunctional circuit design for evaluation in accordance with a static timing analysis is provided herein. The method initially generates a netlist, and then creates a standard delay format (SDF) file from the netlist. The standard delay format file contains occurrence names and delays associated with all elements of the design. The method subsequently selects elements of the design, alters the functionality of each selected element, and alters the standard delay format file entries corresponding to each selected element. The functional alteration of selected elements comprises altering an AND gate to be an OR gate, altering a NAND gate to be a NOR gate, altering an OR gate to be an AND gate, altering a NOR gate to be a NAND gate, altering an XOR to be an XNOR, and/or altering an XNOR to be an XOR in a predetermined manner. The method may accomplish random selection using a random number generator, or alternatively by visually selecting various design elements and altering the functionality of the gate as described. An alternative embodiment is disclosed wherein all elements having similar timing characteristics and different functionality are given identical functionality, such as all AND gates are changed to OR gates, so that all AND and OR gates have OR functionality.

REFERENCES:
patent: 4477904 (1984-10-01), Thorsrud
patent: 4625310 (1986-11-01), Mercer
patent: 5096454 (1992-03-01), Huang
patent: 5210700 (1993-05-01), Tom
patent: 5331570 (1994-07-01), Bershteyn
patent: 5452239 (1995-09-01), Dai et al.
patent: 5475605 (1995-12-01), Lin
patent: 5506852 (1996-04-01), Chakradhar et al.
patent: 5517506 (1996-05-01), Underwood et al.
patent: 5581473 (1996-12-01), Rusu et al.
patent: 5583787 (1996-12-01), Underwood et al.
patent: 5594891 (1997-01-01), Koseko

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