Protection circuits and methods of protecting a semiconductor de

Details Protection circuits and methods of protecting a semiconductor de Protection circuits and methods of protecting a semiconductor de

1998-02-18

2000-07-18

Gaffin, Jeffrey

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

361 56, H02H 904

Patent

active

060915943

ABSTRACT:
Protection circuits and methods of protecting a semiconductor device are provided. According to one aspect, the present invention provides a protection circuit adapted to be coupled to a ground connection, pad and power bus of a semiconductor device, the protection circuit includes electrically coupled first and second transistors adapted to be coupled between a pad and a ground connection, the first and second transistors having a common diffusion region coupling the first transistor with the second transistor in a cascode configuration, the first transistor having a gate adapted to be coupled to a power bus to receive a bias voltage, the power bus being substantially electrically isolated from the pad.

REFERENCES:
patent: 5596474 (1997-01-01), Wada et al.
patent: 5780897 (1998-07-01), Krakauer
patent: 5905614 (1999-05-01), Colombo
patent: 5910874 (1999-06-01), Iniewski et al.
patent: 5930094 (1999-07-01), Amerasekera et al.
Linewidth Control Effects on MOSFET ESD Robustness, S. Voldman, J. Never, S. Holmes, and J. Adkisson, p. 27.1-27.9, EOS/ESD Symposium 96-101. (Date unknown).
ESD Protection In a Mixed-Voltage Interface and Multi-Rail Disconnection Power Grid Environment In 0.50 and 0.25-.mu.m Channel Length CMOS Technologies, Steven H. Voldman, p. 3.4.1-3.4.10, EOS/ESD Symposium 94-125 (Date unknown).

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