Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific voltage responsive fault sensor
Reexamination Certificate
2001-05-22
2004-09-14
Toatley, Jr., Gregory J. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
With specific voltage responsive fault sensor
C361S091100
Reexamination Certificate
active
06791810
ABSTRACT:
RELATED APPLICATION DATA
The present invention claims priority to Japanese Application No. P2000-150350 filed May 22, 2000, which application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a protection circuit of a field effect transistor and a semiconductor device provided with the protection circuit, and particularly to a protection circuit of an FET for protecting a gate electrode or a drain electrode of the field effect transistor, especially a JFET, a MESFET, an HFET, or the like against surge breakdown, and for raising the surge resistance of the FET, in which a diode formed integrally with the FET is made a protection element in order to reduce the number of required process steps, and a semiconductor device provided with such a protection circuit.
2. Description of the Related Art
Since a field effect transistor of a compound semiconductor including a laminate structure of compound semiconductor layers of A GaAs system or the like has a high electron mobility and excellent high frequency characteristics, it is widely used in a field of a high frequency region, such as a portable telephone.
Now, it is known that the surge resistance of a gate electrode or a drain electrode of the compound semiconductor field effect transistor is not so high as to reach a level required for a field effect transistor of a desired use, structure or size.
Especially, in the compound semiconductor field effect transistor, such as a JFET, a MESFET, or an HFET, used for a power amplifier, a bias adjusting circuit of an antenna switch or the like and having a small gate width, for example, a gate width of 10 &mgr;m to 20 &mgr;m, the surge resistance of a gate electrode or a drain electrode is extremely low, and there is a case where the withstanding resistance of the gate electrode or the drain electrode is damaged by a surge voltage of 20 V to 30 V.
The JFET stands for a junction field effect transistor (JFET: Junction Field Effect Transistor) and is an element to perform current modulation by using a pn junction. The MESFET stands for Schottky barrier gate field effect transistor (MESFET: Metal-Semiconductor Field Effect Transistor) and is an element to perform current modulation by using a Schottky junction. The HFET stands for heterojunction field effect transistor (HFET: Heterojunction Field Effect Transistor) and is an element to perform current modulation by using a hetero junction.
Then, in order to raise the surge resistance and to protect the gate electrode of the FET from breakdown, a protection circuit including a protection element and protecting the FET is provided at the gate electrode of the FET.
Here, with reference to
FIGS. 7A and 7B
, a structure of a conventional protection circuit will be described.
FIGS. 7A and 7B
are circuit diagrams showing a protection circuit of a conventional example 1 and a protection circuit of conventional example 2, respectively.
A protection circuit
90
of the conventional example 1 is, as shown in
FIG. 7A
, a circuit in which Vgg connected to a gate electrode of an FET is grounded through a reverse direction diode
92
, and Vgg is also connected to a drain electrode through a forward direction diode
94
.
A protection circuit
96
of the conventional example 2 is, as shown in
FIG. 7B
, a circuit in which Vgg is grounded through a forward direction diode
98
and a reverse direction diode
99
cascade-connected thereto.
However, the above described conventional protection circuits have problems as described below, respectively.
In a field effect transistor such as a GaAs MESFET operated in a high frequency region, a ground line is made large, that is, the ground line is strengthened, so that lowering of high frequency characteristics, that is, lowering of gain in a high frequency region is prevented. However, in the protection circuit of the conventional example 1, as is understood from the structure shown in
FIG. 7A
, it becomes necessary to make terminals for bias adjustment, that is, a gate terminal and a drain terminal approach each other. As a result, there is a problem that to make the gate terminal and the drain terminal approach each other becomes a restriction to a pattern layout, and is not preferable in the pattern layout.
In the protection circuit of the conventional example 2, there is a problem that desired surge resistance can not be secured.
Meanwhile, in the case of a compound semiconductor FET in which a laminate structure of compound semiconductor layers is epitaxially grown on a compound semiconductor substrate, such a step of separately adjusting a channel concentration in order to form a protection element can not be carried out because of the process.
Thus, for example, when the surge resistance of an FET is made to be improved, a distance between a gate and a drain of the FET is set long so that the surge resistance is improved. Like this, in the compound semiconductor FET, there has been no method to improve the surge resistance except for a method of improving the surge resistance by adjusting the layout.
However, in recent years, as a withstand voltage between a gate and a drain of an FET becomes low, a distance between the gate and the drain becomes narrow, and for example, the distance between the gate and the drain is shortened so that it becomes a minimum dimension of design rules of layout.
In such a case, although it is necessary to further reduce a DC withstand voltage of a diode as a protection element, it becomes impossible to narrow a distance between junctions of the diode in the pattern layout.
On the other hand, although the DC withstand voltage can be made low by providing a Schottky electrode or a pn junction electrode in, for example, an n
+
region having a high doping concentration, that is, a high carrier concentration, there is a problem that a leak current is increased at the same time.
SUMMARY OF THE INVENTION
An object of the present invention is therefore to provide a protection circuit of a field effect transistor having a structure which can be fabricated without restricting the pattern layer of the field effect transistor and without increasing process steps.
The present inventor has considered that in order to achieve the above object, necessary conditions for a protection circuit of a field effect transistor, especially a protection circuit of a bias adjusting circuit are three conditions as follows:
(1) leak current of the protection circuit is low in a state where power supply voltage is applied,
(2) withstand voltage is lower than withstand voltage of a transistor or a diode provided at the first of the bias adjusting circuit, and
(3) surge resistance is high.
As a protection circuit of a field effect transistor satisfying the three conditions, the present inventor has conceived and studied a protection circuit in which a plurality of diode units of the same number, in each of which a forward direction diode and a reverse direction diode are made opposite to each other and are connected, are connected in series, and has attained the present invention.
In order to achieve the above object, a protection circuit of a field effect transistor according to the present invention is a protection circuit for protecting a gate electrode of the field effect transistor against surge breakdown, characterized in that
the protection circuit includes a diode array in which a plurality of forward direction first diodes and reverse direction second diodes, the number of which is equal to that of the first diodes, are cascade-connected, and
a gate electrode of the field effect transistor is grounded through the diode array.
In the present invention, the arrangement sequence of the first diodes and the second diodes in the diode array is arbitrary, and for example, the first diode and the second diode cascade-connected thereto constitute a pair, and a plurality of such pairs may be connected in series, or a diode array in which the plurality of first diodes are first cascade-connected may
Nakamura Mitsuhiro
Wada Shin-ichi
Depke Robert J.
Holland & Knight LLP
Kitov Z
Sony Corporation
Toatley , Jr. Gregory J.
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