Protection circuit for output drivers

Details Protection circuit for output drivers Protection circuit for output drivers

1998-07-22

1999-11-16

Sherry, Michael J.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

361 56, H02H 322

Patent

active

059868678

ABSTRACT:
A DRAM output protection circuit (100). A dummy NMOS transistor (116) is connected in parallel with the NMOS output transistor (102). The gate of the dummy transistor (116) is connected through a resistor (122) to ground (108). The resistor 122 value and the gate capacitance (121,127) of the dummy transistor (116) are adjusted to achieve the desired gate matching between the dummy transistor gate (120) and the NMOS output transistor gate (110).

REFERENCES:
patent: 5499152 (1996-03-01), Tamakoshi
"Lateral DMOS Design for ESD Robustness", Texas Instruments, pp. 1-4 (Charvaka Duvvury, Fred Carvajal, Clif Jones and David Briggs), no date.

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