Protection circuit for miller compensated voltage regulators

Details Protection circuit for miller compensated voltage regulators Protection circuit for miller compensated voltage regulators

2002-04-01

2003-10-28

Berhane, Adolf D. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S276000

Reexamination Certificate

active

06639390

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to capacitively compensated voltage regulators, such as Miller compensated voltage regulators, and more particularly relates to a capacitively compensated voltage regulator having improved characteristics in the transition from standby mode to normal mode.
BACKGROUND OF THE INVENTION
Electronic circuits are increasingly used in portable and mobile applications in which low power consumption is highly desirable in order to avoid the necessity of large and bulky battery supplies. Such applications include wireless phones, personal pagers, personal digital assistants, etc.
One way of achieving such low power consumption is to provide a low power mode, which can be a so-called Standby, or, Sleep, mode for the electronic circuit. Standby mode is provided as a general matter by including a module that monitors the use of the circuit and that signals the circuit to change from a normal mode to a Standby mode when the circuit has not been called upon for use after a predetermined time period, or which changes the circuit from a normal mode to a low power mode, if that is all that is required. In response, the circuit changes to a reduced power configuration using a variety of well-known power saving techniques. When the module detects that the circuit is required for use again, the module signals the circuit to return to normal mode.
Capacitively compensated voltage regulators are in widespread use for providing a controlled voltage in a stable circuit. One such circuit finding increased use in low power applications is the Miller compensated low drop-out (“LDO”) voltage regulator. Such voltage regulators have a small difference between the input voltage and the regulated output voltage, and, because of their compensation provide desired circuit stability. An example of a Miller compensated LDO voltage regulator is described in U.S. Pat. No. 6,304,131, entitled “High power supply ripple rejection internally compensated low drop-out voltage regulator using PMOS pass device,” which issued on Oct. 16, 2001, to Mark Wayne Huggins et al., and which is commonly assigned.
However, when attempting to provide a low power mode to capacitively compensated voltage regulators, a problem arises in that in the transition from low power mode to normal mode the compensation capacitor transiently loads the node at which it is located. This problem arises in many capacitively compensated voltage regulators. An example of this problem can be understood by reference to
FIG. 1
, which shows a prior art Miller compensated LDO voltage regulator. In this circuit, being provided with a voltage source V
DD
, a bandgap reference voltage BGR is applied to the input, which is connected to the gate of PMOS transistor MP
1
, and an output voltage is provided at the output node OUT. A load, which may have a capacitive component C
L
and a resistive component R
L
, can be connected between OUT and circuit ground GND. The various components, including as PMOS transistors MP
1
-MP
4
, NMOS transistors MN
1
and MN
2
, current sources and sinks I
1
-I
6
, which may, for example, be current mirrors reflecting a current that is provided by external circuitry, and capacitor C
1
, operate according to well known principles to provide a regulated voltage corresponding to the input voltage BGR at OUT.
The Miller, or compensation, capacitor is C
1
, provided in a feedback path from the output node OUT to node A. The equivalent capacitance at node A is approximately
C
eq=
C
1
·(1
−Av
),  Equation (1)
where Av is the voltage gain between node A and the output, which is a negative quantity.
For the circuit in
FIG. 1
, in the transition from standby mode to normal mode the DC bias voltage at node A increases rapidly, because the current passing through the transistors changes immediately when the circuit changes from normal mode to standby mode. This causes Miller capacitor C
1
to charge to the new DC bias voltage. Changing the voltage at node A very rapidly requires a large amount of current for a short time period. When the common gate transistor MN
2
tries to source all the current needed for this, the voltage at node B collapses. Because current sources cannot drive loads, the amplifier reacts to correct the error.
The buffer transistor MP
3
passes this instantaneous voltage drop to the gate of the pass device MP
4
. In an LDO such as is shown in
FIG. 1
the pass device such as MP
4
can typically conduct from a few to hundreds of milliamps. This instantaneous surge of current causes a charge build-up in the output when there is no load connected, or where there is a small capacitance connected to the output. In fact, the amount of voltage change at the output created by this surge current can be approximated by the following equation:
&Dgr;
V
=(
I
surge×&Dgr;
T
)/
C
load,  Equation (2)
where Isurge is the surge current, &Dgr;T is the interval of the surge and Cload is the capacitance seen at the output.
Solutions to this problem in capacitively compensated voltage regulators are problematic. For example, in Miller compensated LDO voltage regulators the maximum size of the output capacitor is restricted, since the second pole of the system is determined by the size of this capacitor, and too large an output capacitance degrades the phase margin of the LDO. Therefore, a designer cannot simply increase the output capacitor size to reduce this change in output voltage until the specifications have been met. Furthermore, increasing the size of the output capacitor can also result in an increase in the cost of the product including the circuit. However, as mentioned above, while of particular concern in Miller compensated LDOs, numerous architectures and implementations are known to provide capacitively compensated voltage regulation, and have the same problem of overshoot.
Therefore, it would be desirable to have a capacitively compensated voltage regulator circuit that avoids the problems discussed above.
SUMMARY OF THE INVENTION
In accordance with the present invention there is provided a capacitively compensated voltage regulator, adapted to be supplied with power from a voltage supply, and having an input port and an output port. The voltage regulator includes a voltage regulation circuit responsive to a reference voltage at the input port to provide a regulated voltage at the output port, including a compensation capacitor having a plate connected to a node internal to the voltage regulator, and including a current source coupled between the voltage supply and the internal node. The voltage regulator also includes a low power control circuit responsive to a low power command signal. The low power control circuit includes a delay circuit responsive to a transition in the level of the low power command signal to generate a low power control signal for a predetermined time period after said transition, and also a bypass circuit coupled between the internal node and the voltage supply, responsive to the low power control signal to provide, for the predetermined time period, a current higher than the current provided by the current source, and otherwise to provide substantially no current. By the action of the standby control circuit a voltage overshoot or surge at the output port of the voltage regulator circuit is avoided.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.


REFERENCES:
patent: 4908566 (1990-03-01), Tesch
patent: 5850139 (1998-12-01), Edwards
patent: 5867015 (1999-02-01), Corsi et al.
patent: 6084475 (2000-07-01), Rincon-Mora
patent: 6188211 (2001-02-01), Rincon-Mora et al.
patent: 6246221 (2001-06-01), Xi
patent: 6278320 (2001-08-01), Vu
patent: 6300749 (2001-10-01), Castelli et al.
patent: 6304131 (2001-10-01), Huggins et al.
patent: 6448750 (2002-09-01), Shor et al.

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