Protection circuit for an LCD controller IC

Details Protection circuit for an LCD controller IC Protection circuit for an LCD controller IC

1999-06-08

2002-02-26

Huynh, Kim (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000, C257S355000

Reexamination Certificate

active

06351362

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a protection circuit for an LCD controller which is used in a module having a panel mounted thereto.
With respect to electro-static breakdown, various kinds of models are well known (refer to an article of IEICE Technical Report, ED 94-58 (1994), pp. 25 to 30 for example). The typical ones are an HBM (Human Body Model) and an MM (Machine Model). In the case of the HBM, the pulse width relating to the movement of the electric charges is 10E−8 sec, while in the case of the MM, the pulse width relating to the movement of the electric charges is in the range of 10E−10 to 10E−9 sec.
Conventionally, there has been used a protection circuit having only a first normally-off type NMOS transistor
2
and a second normally-off type NMOS transistor
3
both of which are connected to an input pad
1
as shown in FIG.
2
.
In the case of an LCD controller which is used in a module having a panel mounted thereto, the module is charged with the electric charges, and hence the model of a small capacity which is represented by a CDM (Charged Device Model) is charged with the electric charges. As a result, the movement of electric charges is more rapidly carried out compared with those of the HBM and the MM, and becomes on the order of picoseconds (in the range of 10E−12 to 10E−11 sec).
In the prior art, since the movement of electric charges is extremely rapid, the movement speed of the electric charges in an IC varies depending on the wiring capacity, the substrate resistance, the well resistance and the like. As a result, an electric field is applied across the gate oxide film of the MOS transistor constituting the input circuit and the gate oxide film is electro-statically broken down. The breakdown of the gate oxide film due to the rapid movement of the pulse becomes more and more remarkable as the scale down (shrink) has progressed to reduce the film thickness of the gate oxide film.
SUMMARY OF THE INVENTION
In order to prevent an electric field which will damage a gate oxide film from being applied across the gate oxide film, first and second normally-off type NMOS transistors are both provided between an input gate circuit and a resistor, and a third normally-off type PMOS transistor and a fourth normally-off type NMOS transistor are both provided right before an input circuit which is arranged after the resistor.
When an electric field is applied across a gate oxide film, the electric charges can be made to escape in the form of an avalanche breakdown current of diodes which the third and fourth transistors have or drains of the transistors, or in the form of a tunnelling current between bands, so that the electric field is prevented from being applied across the gate oxide film of the input circuit to avoid the gate oxide film from resulting in dielectric breakdown.


REFERENCES:
patent: 5051860 (1991-09-01), Lee et al.
patent: 5159518 (1992-10-01), Roy
patent: 5631793 (1997-05-01), Ker et al.
patent: 5751525 (1998-05-01), Olney
patent: 5946175 (1999-08-01), Yu

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