Protection circuit and semiconductor device

Details Protection circuit and semiconductor device Protection circuit and semiconductor device

2001-10-31

2003-07-22

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Device protection

C257S355000, C257S356000, C257S174000, C257S357000, C257S358000, C257S359000

Reexamination Certificate

active

06597021

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a protection circuit for use in protection of a MIS semiconductor device fabricated using a CMOS process from a semiconductor device from an excessively high voltage, and a semiconductor device including a protection circuit.
2. Description of the Related Art
Semiconductor devices fabricated with a CMOS process are generally less resistant to static electricity. In order to protect a semiconductor device from being damaged by static electricity, a protection circuit is typically provided at an external input-output terminal of the semiconductor device. A thyristor is widely used in such a protection circuit. A thyristor is a semiconductor device including two or more PN junctions. A fundamental structure of a thyristor is shown in FIG.
1
.
FIG. 1
is a cross-sectional view showing a fundamental thyristor taken along a normal direction to a substrate surface. This fundamental thyristor includes a P-type silicon substrate
1
. A low-concentration N-type semiconductor region
3
and a low-concentration P-type semiconductor region
4
are provided side by side in a horizontal direction on the silicon substrate
1
. A high-concentration N-type semiconductor region
5
and a high-concentration P-type semiconductor region
7
are provided on the low-concentration N-type semiconductor region
3
and are separated by an isolation region
2
. A high-concentration N-type semiconductor region
6
and a high-concentration P-type semiconductor region
8
are provided on the low-concentration P-type semiconductor region
4
and are separated by the isolation region
2
. The isolation region
2
is also provided on an interface between the low-concentration N-type semiconductor region
3
and the low-concentration P-type semiconductor region
4
to separate the high-concentration P-type semiconductor region
7
and the high-concentration N-type semiconductor region
6
from each other.
Thus, the thyristor shown in
FIG. 1
has a P-N-P-N structure. An anode terminal T
1
is connected to the high-concentration N-type semiconductor region
5
and the high-concentration P-type semiconductor region
7
, and a cathode terminal T
2
is connected to the high-concentration N-type semiconductor region
6
and the high-concentration P-type semiconductor region
8
. Note that the high-concentration P-type semiconductor region
7
and the high-concentration N-type semiconductor region
6
which are separated by the isolation region
2
are referred to as an anode and a cathode, respectively.
FIG. 2
is a graph showing the current-voltage characteristics of a typical thyristor where the voltage applied to the anode is changed while the cathode is set to be held at a reference potential (0 V). As shown in
FIG. 2
, the thyristor can allow a large amount of current to flow therethrough with an increase in voltage in the positive direction once it is switched ON. The thyristor can also allow a large amount of current to flow therethrough with an increase in voltage in the negative direction due to the forward direction characteristics of the PN junction. Therefore, thyristors are often used as static electricity protection circuits.
Note electrostatic discharge is caused by combining any two terminals having positive and negative polarities. Therefore, the static electricity protection circuit needs to be capable of allowing a sufficient amount of discharge current to flow between any two terminals.
A conventional protection circuit for such electrostatic discharge will be described with reference to FIG.
3
.
FIG. 3
is a block diagram showing a semiconductor device including a conventional static electricity protection circuit. In this semiconductor device, a protection circuit is connected to an external input-output terminal PAD. In the protection circuit, a P-type MOS transistor PMOS is provided between the external input-output terminal PAD and a power supply terminal VDD, and a resistance portion R
1
and an N-type MOS transistor NMOS are provided between the P-type MOS transistor PMOS and a ground terminal VSS. A power supply line is represented by line a-b in
FIG. 3
, and a ground line is represented by line c-d in FIG.
3
.
A first thyristor SCR
1
is provided between the external input-output terminal PAD and the ground line c-d. The anode portion of the first thyristor SCR
1
is connected to the external input-output terminal PAD, and the cathode portion is connected to the ground line c-d. A second thyristor SCR
2
is provided between the power supply line a-b and the ground line c-d. The anode portion of the second thyristor SCR
2
is connected to the power supply line a-b, and the cathode portion is connected to the ground line c-d.
An internal circuit
50
is connected via a resistance portion R
2
to the external input-output terminal PAD. The internal circuit
50
is also connected to the power supply terminal VDD and the ground terminal VSS.
In the exemplary semiconductor device shown in
FIG. 3
, the P-type MOS transistor PMOS functions as an output transistor. If the P-type MOS transistor PMOS functions as an input transistor, typically, the gate thereof is connected to the internal circuit
50
side of the resistance portion R
2
.
The resistance value of the resistance portion R
1
connected to the N-type MOS transistor NMOS is about 10&OHgr;, which is similar to the resistance value of a typical resistance portion connected to an N-type MOS transistor. In the semiconductor device shown in
FIG. 3
, a connection node between the P-type MOS transistor PMOS and the N-type MOS transistor NMOS is connected via the resistance portion R
2
to an input portion of the internal circuit
50
. Alternatively, the internal circuit
50
may be connected via the resistance portion R
2
between the resistance portion R
1
and the N-type MOS transistor NMOS.
The resistance portion R
2
connected to the input side of the internal circuit
50
is provided so as to protect the gate of the internal circuit
50
, and has a resistance value of about 150&OHgr; to about 400&OHgr;. If the external input-output terminal PAD is used as an input terminal of the internal circuit
50
, the resistance portion R
2
may be provided between the connection node between the P-type MOS transistor PMOS and the N-type MOS transistor NMOS, and the external input-output terminal PAD. If the external input-output terminal PAD is used as an output terminal of the internal circuit
50
, an output current cannot be obtained and therefore the resistance portion R
2
cannot be provided between the power supply terminal VDD and the external input-output terminal PAD.
As described above, a thyristor has a high capability of discharging currents in both positive and negative directions. Therefore, in the semiconductor device shown in
FIG. 3
, the second thyristor SCR
2
functions as a protection element against electrostatic discharge conducted between the power supply terminal VDD and the ground terminal VSS, so that the semiconductor device exhibits a high level of static electricity endurance. The first thyristor SCR
1
functions as a protection element against electrostatic discharge conducted between the external input-output terminal PAD and the ground terminal VSS, so that the semiconductor device exhibits a high level of static electricity endurance.
Next, electrostatic discharge conducted between the external input-output terminal PAD and the power supply terminal VDD will be described.
FIG. 4
is a cross-sectional view showing a configuration of the P-type MOS transistor PMOS of the semiconductor device shown in FIG.
3
. The P-type MOS transistor PMOS shown in
FIG. 4
includes a P-type silicon substrate
9
. A low-concentration N-type semiconductor region
10
is provided on the P-type silicon substrate
9
. A gate polysilicon
14
is provided via a gate oxide film
40
on the low-concentration N-type semiconductor region
10
. A high-concentration P-type semiconductor region
13
and a high-concentration P-type semiconductor region

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