Protecting proprietary asic design information using boundary sc

Details Protecting proprietary asic design information using boundary sc Protecting proprietary asic design information using boundary sc

1996-03-14

1997-06-10

Beausoliel, Jr., Robert W.

Excavating

371 251, 364488, 364489, G01R 3128

Patent

active

056383800

ABSTRACT:
A method of choosing non-scan I/O nodes to replace with scan I/O nodes so as to allow the greatest amount of proprietary information to be removed from an ASIC core netlist which is to be supplied to an ASIC customer, includes the steps of assigning weights to core gates based upon how competitively sensitive those gates are determined to be, assigning a value to each non-scan I/O node based upon the sum of weights of all gates to which the I/O node is connected, and replacing the non-scan I/O node having the greatest value with a scan node. Gates that are within the timing shell are assigned a weight of zero. I/O nodes that are performance critical are assigned a value of zero, and the weights of all gates connected to such performance-critical I/O's are also set to zero. The I/O node selection process is iterative, with the weight of a gate being set to zero when it is connected to more non-scan I/O nodes than are remaining to be chosen.

REFERENCES:
patent: 5012471 (1991-04-01), Powell et al.
patent: 5132974 (1992-07-01), Rosales
patent: 5291495 (1994-03-01), Udell
patent: 5396435 (1995-03-01), Geinetti
patent: 5414716 (1995-05-01), Bershteyn
patent: 5524082 (1996-06-01), Horstmann et al.
International Test Conference 1991, Paper 14-2, Hierarchical Test Program Development For Scan Testable Circuits, pp. 375-384.

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