Protected dual-voltage microcircuit power arrangement

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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Details

C361S018000, C361S058000, C361S118000

Reexamination Certificate

active

06700763

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to integrated circuits and more particularly to microcircuits requiring two or more different energizing voltages.
BACKGROUND OF THE INVENTION
A continuing need for higher processing speed has accompanied the advent of high-speed digital processing equipment. The higher processing speed, in turn, has tended to increase the heat dissipated internally in microcircuits which implement the processing. This heat, in turn, tends to raise the temperatures of the microcircuits. The reliability of solid-state microcircuits depends to a substantial degree on the temperature at which they operate. Even short periods of operation at temperatures elevated above the maximum temperature rating of a given microcircuit can substantially reduce its reliability. For this reason, a great deal of attention is directed toward heat removal from microcircuits, to the extent that liquid coolants have been proposed for flow adjacent to solid-state chips, as described in U.S. Pat. No. 6,388,317, issued May 14, 2002 in the name of Reese.
One of the techniques which has been applied for reducing the temperature of high-density microcircuits is to use lower power-supply or energizing voltages for those “core” portions of the microcircuit which are most densely packed or which operate at the highest switching speed, relative to the energizing voltage applied to “peripheral” circuits on the microcircuit. This gives rise to “dual-voltage” microcircuits, which require two or more different energizing voltages. Dual-voltage microcircuits, as one might expect, require separate power supplies to provide the direct voltages which are required for the core and peripheral portions of the microcircuit. A common type of dual-voltage microcircuit requires both 2.5-volt and 3.3-volt sources.
The provision of many functions on a microcircuit requires that the spacing between conductors in the microcircuit be very small, and also that the solid-state elements to which the conductors connect be very small. This small size contributes to the usefulness of the microcircuit, and also allows fast operation. The close spacings and small size, however, are disadvantageous in that the spacings are so small that damaging voltage breakdown or flashover may occur with relatively low voltages. For this reason, electromagnetic surge and/or over-voltage protection is often provided by non-linear devices in the form of diodes, diode-connected field-effect transistors (FETs), or other unidirectional current conducting devices, as described, for example, in U.S. Pat. No. 5,708,550 issued Jan. 13, 1998 in the name of Avery; U.S. Pat. No. 6,040,968, issued Mar. 21, 2000 in the name of Duvvury et al.; U.S. Pat. No. 6,043,539, issued Mar. 28, 2000 in the name of Sugasawara; and U.S. Pat. No. 6,060,752, issued May 9, 2000 in the name of Williams. These nonlinear devices are often connected to the various electrodes of the microcircuit which provide connection to the outside world, so as to damp surges and bypass over-voltages around those portions of the microcircuit which are to be protected. One known scheme is to connect unidirectional current conducting device(s) in an antiparallel manner between a first voltage input electrode of a microcircuit and a second voltage input electrode, as described in the Duvvury et al. patent, where the supply voltages have different values. The Duvvury et al. arrangement has the effect of “connecting” the voltages of the electrodes together whenever the voltage of one source attempts to deviate from the other by more than the offset voltage of the unidirectional current conducting devices.
Improved dual-supply arrangements are desired.
SUMMARY OF THE INVENTION
A power supply protection apparatus according to an aspect of the invention comprises a first power supply for generating a first supply output level to energize a first load circuit, and a second power supply for generating a second supply output level to energize a second load circuit. A clamp circuit is responsive to a signal that is indicative of the second supply output level for clamping the first supply output level, when both a difference between the first and second supply output levels is outside a first normal operation range of values and the second supply output level is within a second normal operation range of values. The clamping of the first supply output level is prevented, when the difference is within the first normal operation range of values. A detector is responsive to the second supply output level indicative signal and is coupled to the first power supply for varying the first supply output level to prevent the clamping of the first supply output level, when the second supply output level is outside the second normal operation range of values.
In one version of the apparatus, the clamp circuit includes a switch.
In another version of the apparatus, the clamp circuit includes one of a rectifier and a diode.
In one avatar of the apparatus, the first load circuit forms a first stage and the second load circuit forms a second stage of a common integrated circuit.
In another avatar of the apparatus, the first power supply level is disabled, when the second supply output is outside the second normal operation range of values.


REFERENCES:
patent: 5266849 (1993-11-01), Kitahara et al.
patent: 5708550 (1998-01-01), Avery
patent: 5774318 (1998-06-01), McClure et al.
patent: 5933025 (1999-08-01), Nance et al.
patent: 6040968 (2000-03-01), Duvvury et al.
patent: 6043539 (2000-03-01), Sugasawara
patent: 6060752 (2000-05-01), Williams
patent: 6154845 (2000-11-01), Ilkbahar et al.
patent: 6189107 (2001-02-01), Kim et al.
patent: 6218889 (2001-04-01), Fujiki et al.
patent: 6269011 (2001-07-01), Ohshima
patent: 6313615 (2001-11-01), Fayneh et al.
patent: 6335637 (2002-01-01), Correale et al.

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