Electric lamp and discharge devices: systems – Current and/or voltage regulation
Reexamination Certificate
2000-02-18
2001-03-20
Vu, David (Department: 2821)
Electric lamp and discharge devices: systems
Current and/or voltage regulation
C315S307000, C315SDIG004
Reexamination Certificate
active
06204613
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to dimming electronic ballasts used to power gas discharge lamps. Specifically, this invention pertains to a 0-10 volt dimming control interface for an electronic ballast that includes components that will prevent the dimming control interface from being damaged if it is accidentally connected to an external AC power source. More specifically, the dimming control interface of the present invention includes circuits that limit voltages and currents present in the dimming control interface circuit to safe levels when the external AC power source is connected to the dimming interface circuit.
Generally, a 0-10 volt dimming control interface is designed to be connected to a DC control voltage, while the ballast itself is designed to be connected to an external AC power source. A conventional 0-10 volt control interface is designed to deliver a small current preferably ranging from about 300 &mgr;A to 500 &mgr;A. Consequently, a typical DC control voltage may be obtained from a variable resistor, a shunt controller, or a more sophisticated light-level controller. Shunt controllers control ballasts by setting the voltage between the control input terminals to a level ranging from 0 volts to 10 volts. If the shunt controller is disconnected from the dimming control interface, the open-circuit voltage between the control input terminals will rise to approximately 10 volts.
To allow these connections, dimming ballasts usually include a pair of dimming control input terminals designed to be connected to the DC control voltage, and a pair of AC power input terminals designed to be connected to the external AC power source. Sometimes, however, the AC power source is accidentally connected to the dimming control input terminals rather than the AC power input terminals. As a result, the dimming control interface and the ballast may be damaged by excessive currents and voltages generated by the AC power source. Replacement of the damaged dimming control interface and/or the ballast is an expensive proposition. Thus, there is a need for a dimming control interface that may be connected to a DC control voltage, as well as, an external AC power source without being damaged.
To complicate matters even more, a dimming control interface may be connected to several different ballasts through a single pair of dimming control input terminals. When the external AC power source is connected to such a dimming control interface, excessive currents and voltages generated by the AC power source may damage several ballasts. Replacement of multiple dimming control interfaces and/or ballasts is accordingly more expensive and undesirable. Thus, there is an additional need for a dimming control interface that may be connected to an external AC power source without being damaged.
Although dimming control interface circuits are well known in the art, there are no known dimming control interfaces that are capable of withstanding a sustained connection to an external AC power source without being damaged. For example, one known dimming control interface is described in U.S. Pat. No. 5,751,188 issued to Mortimer on May 12, 1998 and entitled “Universal Input Dimmer Interface.” This patent teaches a dimming control interface that may be connected to an external DC control voltage or an external pulse-width modulated control voltage. In either case, the dimming control interface includes circuitry for generating an electrically isolated control voltage at output terminals on the dimming control interface in response to the input control voltage applied at input terminals on the dimming control interface, whether the input control voltage is the DC control voltage or the pulse-width modulated control voltage. This patent fails to teach or suggest the use of any circuits for the purpose of limiting currents and voltages present in the dimming ballast when an external AC voltage is applied to the dimming control input terminals.
Another example is described in U.S. Pat. No. 5,583,402 issued to Moisin et al. on Dec. 10, 1996 and entitled “Symmetry Control Circuit and Method.” This patent also teaches a dimming interface circuit designed to be connected to either a DC control voltage or a pulse-width modulated voltage signal. As was the case with the '188 patent, this patent fails to teach or suggest the use of circuits designed to limit currents and voltages present in the dimming ballast when an AC power source is connected.
Two additional examples of dimming control interfaces are described in U.S. Pat. No. 5,089,751 issued to Wong et al. on Feb. 18, 1992 and entitled “Fluorescent Lamp Controllers with Dimming Control,” and U.S. Pat. No. 5,003,230 issued to Wong et al. on Mar. 26, 1991 and entitled “Fluorescent Lamp Controllers with Dimming Control.” Neither of these patents teach a dimming control interface that includes protection from connection of the dimming input terminals to an external AC power source.
In addition, there are two known commercial dimming control interfaces. A portion of a one such prior-art dimming control interface circuit is shown in
FIG. 1. A
small-signal PNP transistor Q
1
is connected to a biasing circuit (not shown) so that the transistor will supply about 400 &mgr;A current to a shunt controller (not shown) connected between control input terminals J
1
and J
2
. A zener diode D
1
prevents the voltage between terminals J
1
and J
2
from rising above about 10 V if no shunt controller is connected to the circuit. An isolated coupling circuit (not shown) may be connected between terminals J
3
and J
5
. The isolated coupling circuit sends a dimming control signal to a ballast inverter circuit (not shown). A resistor R
1
provides protection for the interface circuit if the control terminals should accidentally be connected to a low voltage source such as a 24 VAC control line. R
1
typically has a value of about 1 k&OHgr;, so the 0.4 V voltage drop due to the 400 &mgr;A current is small in comparison with 10 V, and can be compensated for. It is impractical to make R
1
large enough in value to withstand ac power line voltages because the voltage that would then be dropped across it due to the 400 &mgr;A current would be large in comparison with 10 V.
A portion of another commercial dimming control interface is shown in
FIG. 2. A
floating 12 V dc power supply (not shown) is connected between terminals J
14
and J
15
, with the positive terminal connected to J
14
. Resistors R
2
and R
3
have a value of 10 k&OHgr;. They supply current to control input terminal J
11
through a high voltage diode D
2
. A high-voltage N-Channel power MOSFET transistor Q
2
is biased on by resistors R
2
and R
3
when terminal J
11
is positive with respect to J
12
, which is the case during normal operation. During normal operation, the voltage between terminals J
13
and J
15
is about 0.6 V less than the voltage between terminals J
11
and J
12
. The voltage between terminals J
13
and J
15
is coupled to a regulator circuit consisting of an operational amplifier U
1
, resistors, R
4
, R
5
and R
6
, a capacitor, C
1
, and a current sensor circuit
10
. The input terminals of an optocoupler (not shown) are connected between terminals J
16
and J
15
. The current sensor provides a signal that is proportional to the lamp current. This signal provides negative feedback even though it is connected to the positive terminal of U
1
because the optocoupler is connected to the ballast inverter (not shown) in a way that decreases lamp current when the input current to the optocoupler increases.
If the voltage between terminals J
11
and J
12
becomes negative, Q
2
is turned off, and this protects the regulator circuit. If the voltage between terminals J
11
and J
12
becomes greater than about 11 V, diode D
2
becomes reverse biased, and this also protects the regulator circuit. If the blocking capabilities of D
2
and Q
2
were each about 600 V, then the regulator circuit would be protected if terminals J
11
and J
12
were connected acros
Brantley Larry W.
Vu David
Waddey & Patterson
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