Property generating apparatus, property generating method...

Details Property generating apparatus, property generating method... Property generating apparatus, property generating method...

2011-06-28

2011-06-28

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S104000

Reexamination Certificate

active

07971163

ABSTRACT:
Disclosed is a property generating apparatus which generates a property representing a specification of an integrated circuit and verifying design information on the integrated circuit described in RTL (Register Transfer Level). The property generating apparatus includes: a storage unit, which stores a register name to identify a register; an address expanding unit, which expands property abbreviated description information on a group of registers including the register, and generates a group of addresses; an RTL analysis unit, which selects a group of register names from the register name stored in the storage unit; and a property generation unit, which generates the property by correlating the group of addresses with the group of register names.

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Japanese Office Action for JP2008-048382 issued Mar. 10, 2010.

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