PROM electrically written by solid phase epitaxy

Details PROM electrically written by solid phase epitaxy PROM electrically written by solid phase epitaxy

1978-04-06

1979-11-13

Larkins, William D.

Metal treatment

Stock

Ferrous

29584, 148 15, 148175, 357 2, 357 15, 357 67, 365105, G11C 1136, H01L 2120

Patent

active

041745213

ABSTRACT:
A memory cell, having a doped amorphous silicon layer, is formed on a thin layer of silicon alloy which is on a single crystal silicon substrate. The cell is programmed by applying a voltage between a surface contact and the substrate to cause a crystal column to form in the amorphous layer between the substrate and the contact by solid-phase epitaxial growth. A diode is formed between the contact and the substrate by the selection of impurity levels and conductivity type of the amorphous layer and substrate and the selection of the silicon alloy. The cross-sectional area of the column is selectable to provide a multi storage level cell.

REFERENCES:
patent: 3413157 (1968-11-01), Kuiper
patent: 3525146 (1970-08-01), Hayashida et al.
patent: 3877049 (1975-04-01), Buckley
patent: 3918032 (1975-11-01), Nicolaides
patent: 4012235 (1977-03-01), Mayer et al.
Pretorius et al., Applied Physics Letters, vol. 29, No. 9, Nov. 1, 1976, pp. 598-600.
Feldman et al., Journal of Non-Crystalline Solids (2), (1970), pp. 82-90.
Brodsky et al., IBM Technical Disclosure Bulletin, vol. 13, No. 11, Apr. 1971, P3223.

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