Progressive scan video processor having parallel organized memor

Details Progressive scan video processor having parallel organized memor Progressive scan video processor having parallel organized memor

1984-08-31

1986-04-01

Britton, Howard W.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358 21R, 358242, H04N 701, H04N 568

Patent

active

045801630

ABSTRACT:
A processor, for providing a double line-rate video output signal comprising alternating received lines and interpolated lines, comprises three memories. As each line of incoming video signal is stored in one of the three memories, at a given clock rate the remaining two memories are read at double the write clock rate. A single averaging circuit, having inputs selectively coupled to the memories, interleaves non-interpolated time compressed lines of video obtained from one of the two memories being read with time-compressed lines of video obtained by interpolation from both of the two memories being read to provide a processed video output signal. The "write-one read-two" memory organization enables concurrent interpolation and speed-up of the video signal thereby minimizing potential clock timing problems inherent in progressive scan systems of the type where interpolation is provided separately either before or after video speed-up.

REFERENCES:
patent: 3830971 (1974-08-01), van de Polder
patent: 4322750 (1982-03-01), Lord
patent: 4364090 (1982-12-01), Wendland
patent: 4400719 (1983-08-01), Powers
patent: 4415931 (1983-11-01), Dischert
patent: 4480267 (1984-10-01), van den Auoort
patent: 4484188 (1984-11-01), Ott
patent: 4539592 (1985-09-01), Tanaka

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